Datasheet > MB9BF505NAPMC-G-JNE2

MB9BF505NAPMC-G-JNE2

更新时间： 2024-11-08 00:39:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		微控制器
页数	文件大小	规格书
115页	1870K
描述
32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller

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MB9B500B Series

32-bit Arm^®Cortex^®-M3

FM3 Microcontroller

The MB9B500B Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded

control applications.

The MB9B500B Series are based on the Arm^®Cortex^®-M3 Processor and on-chip Flash memory and SRAM, and peripheral

functions, including Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I²C, LIN).

The products which are described in this data sheet are placed into TYPE0 product categories in "FM3 Family Peripheral Manual".

Features

[USB Device]

32-bit Arm^®Cortex^®-M3 Core

 USB2.0 Full-Speed supported

 Processor version: r2p0

 Max. 6 EndPoint supported

 EndPoint 0 is control transfer

 EndPoint 1-5 can be selected bulk-transfer or interrupt-

transfer

 Up to 80 MHz Frequency Operation

 Memory Protection Unit (MPU): improve the reliability of an

embedded system

 Integrated Nested Vectored Interrupt Controller (NVIC): 1

NMI (non-maskable interrupt) and 48 peripheral interrupts

and 16 priority levels

 EndPoint 1-5 is comprised Double Buffer

[USB Host]

 24-bit System timer (Sys Tick): System timer for OS task

 USB2.0 Full/Low speed supported

management

 Bulk-transfer and interrupt-transfer and Isochronous-

transfer support

On-chip Memories

 USB Device connected/dis-connected automatically detect

 IN/OUT token handshake packet automatically

 Max.256-byte packet-length supported

[Flash memory]

 Up to 512 Kbyte

 Read cycle: 0wait-cycle@up to 60 MHz, 2wait-cycle* above

*: Instruction pre-fetch buffer is included. So when CPU

access continuously, it becomes 0wait-cycle

 Wake-up function supported

CAN Interface (Max. 2 channels)

 Compatible with CAN Specification 2.0A/B

 Maximum transfer rate: 1 Mbps

 Built-in 32 message buffer

 Security function for code protection

[SRAM]

This series contain a total of up to 64 Kbyte on-chip SRAM.

This is composed of two independent SRAM(SRAM0,

SRAM1). SRAM0 is connected to I-code bus and D-code bus

of Cortex-M3 core. SRAM1 is connected to System bus.

Multi-function Serial Interface (Max. 8 channels)

 SRAM0: Up to 32 Kbyte

 SRAM1: Up to 32 Kbyte

 4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels

without FIFO (ch.0-ch.3)

 Operation mode is selectable from the followings for each

channel.

 UART

 CSIO

 LIN

USB Interface

USB interface is composed of Device and Host.

PLL for USB is built-in, USB clock can be generated by

multiplication of Main clock.

 I²C

Cypress Semiconductor Corporation

Document Number: 002-05607 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 24, 2017

12 3 4 5 6 7...115

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与MB9BF505NAPMC-G-JNE2相关器件

型号	品牌	获取价格	描述	数据表
MB9BF505NB	SPANSION	获取价格	This document states the current technical specifications regarding
MB9BF505NBBGL-GK6E1	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF505NBGL-GE1	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF505NBPMC	CYPRESS	获取价格	RISC Microcontroller, 32-Bit, FLASH, CORTEX-M3 CPU, 80MHz, CMOS, PQFP100,
MB9BF505NBPMC-G-JNE2	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF505NPMC-G-JNE2	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF505RAPMC-G-JNE2	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF505RB	SPANSION	获取价格	This document states the current technical specifications regarding
MB9BF505RBPMC-G-JNE2	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller
MB9BF505RPMC-G-JNE2	CYPRESS	获取价格	32-bit ArmÂ® CortexÂ®-M3 FM3 Microcontroller

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