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MB90F351APMC PDF预览

MB90F351APMC

更新时间: 2024-01-15 12:06:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟微控制器外围集成电路装置
页数 文件大小 规格书
83页 1275K
描述
F2MC-16LX 16-bit Microcontroller

MB90F351APMC 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:LQFP, QFP64,.55SQReach Compliance Code:compliant
风险等级:5.63具有ADC:YES
地址总线宽度:22位大小:16
边界扫描:NO最大时钟频率:24 MHz
DAC 通道:NODMA 通道:YES
外部数据总线宽度:16格式:FIXED POINT
集成缓存:NOJESD-30 代码:S-PQFP-G64
长度:12 mm低功率模式:YES
DMA 通道数量:16外部中断装置数量:8
I/O 线路数量:49串行 I/O 数:1
端子数量:64计时器数量:18
片上数据RAM宽度:8片上程序ROM宽度:8
最高工作温度:125 °C最低工作温度:-40 °C
PWM 通道:NO封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP64,.55SQ
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
RAM(字节):4096RAM(字数):65536
ROM可编程性:FLASH座面最大高度:1.7 mm
速度:24 MHz最大压摆率:70 mA
最大供电电压:5.5 V最小供电电压:4 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:12 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER

MB90F351APMC 数据手册

 浏览型号MB90F351APMC的Datasheet PDF文件第2页浏览型号MB90F351APMC的Datasheet PDF文件第3页浏览型号MB90F351APMC的Datasheet PDF文件第4页浏览型号MB90F351APMC的Datasheet PDF文件第5页浏览型号MB90F351APMC的Datasheet PDF文件第6页浏览型号MB90F351APMC的Datasheet PDF文件第7页 
MB90350 Series  
F2MC-16LX 16-bit Microcontroller  
The MB90350-series with 1 channel FULL-CAN interface and Flash ROM is especially designed for automotive and industrial appli-  
cations. Its main feature is the on-board CAN interface, which conforms to V2.0 Part A and Part B, while supporting a very flexible  
message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35μm CMOS technology,  
Cypress now offers on-chip Flash-ROM program memory up to 128 Kbytes.  
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a major advantage in terms  
of EMI and power consumption.  
The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external 4 MHz clock. Also,  
the clock monitor function can monitor main clock and sub clock independently.  
As the peripheral resources, the unit features a 4-channel Output Compare Unit, 6-channel Input Capture Unit, 2 separate 16-bit  
freerun timers, 2-channel UART and 15-channel 8/10-bit A/D converter.  
Features  
Clock  
Increased processing speed  
Built-in PLL clock frequency multiplication circuit  
4-byte instruction queue  
Selection of machine clocks (PLL clocks) is allowed among  
frequencydivisionbytwoonoscillationclock,andmultiplication  
of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock,  
4 MHz to 24 MHz).  
Powerful interrupt function  
Powerful 8-level, 34-condition interrupt feature  
Up to 8 channels external interrupts are supported.  
Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock  
divided by two) is allowed. (devices without S-suffix only)  
Automatic data transfer function independent of CPU  
Extended intelligent I/O service function (EI2OS) : up to 16  
channels  
Minimum execution time of instruction : 42 ns (when operating  
with 4-MHz oscillation clock, and 6-time multiplied PLL clock).  
DMA: up to 16 channels  
Built-in clock modulation circuit  
Low power consumption (standby) mode  
16 Mbytes CPU memory space  
Sleep mode (a mode that halts CPU operating clock)  
24-bit internal addressing  
Main timer mode (a timebase timer mode switched from the  
main clock mode)  
Clock monitor function (MB90x356x and MB90x357x  
only)  
PLLtimer mode (a timebase timer mode switched from the PLL  
clock mode)  
Main clock or sub clock is monitored independently.  
Internal CR oscillation clock (100 kHz typical) can be used as  
sub clock.  
Watch mode (a mode that operates sub clock and watch timer  
only)  
Instruction system best suited to controller  
Wide choice of data types (bit, byte, word, and long word)  
Wide choice of addressing modes (23 types)  
Stop mode (a mode that stops oscillation clock and sub clock)  
CPU intermittent operation mode  
Process  
Enhanced multiply-divide instructions with sign and RETI  
instructions  
CMOS technology  
I/O port  
Enhanced high-precision computing with 32-bit accumulator  
General-purpose input/output port (CMOS output)  
49 ports (devices without S-suffix : devices that correspond  
to sub clock)  
Instruction system compatible with high-level  
language (C language) and multitask  
51 ports (devices with S-suffix : devices that do not corre-  
spond to sub clock)  
Employing system stack pointer  
Enhanced various pointer indirect instructions  
Barrel shift instructions  
Cypress Semiconductor Corporation  
Document Number: 002-07872 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 31, 2017  

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