5秒后页面跳转
捷配首页

Datasheet > 电信电路 > 蜂窝电话电路> MAX5865E/D
MAX5865E/D PDF预览

MAX5865E/D

更新时间： 2024-02-07 18:25:04
品牌 Logo 应用领域
美信 - MAXIM 电信集成电路蜂窝电话电路电信电路
页数 文件大小 规格书
26页 2143K
描述
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End

阅读下载

获取价格

MAX5865E/D 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFN
包装说明：7 X 7 MM, 0.80 MM HEIGHT, TQFN-48针数：48
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.12Is Samacsys：N
模拟输入最大值：1.5 V输入类型：DIFFERENTIAL
JESD-30 代码：S-XQCC-N48JESD-609代码：e0
长度：7 mm信道数量：2
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出：VOLTAGE输出代码：OFFSET BINARY
最大输出电压：3 V封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC48,.27SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.8,3.3 V
认证状态：Not Qualified分辨率：8 µm
座面最大高度：0.8 mm子类别：Codecs
标称供电电压：3 V表面贴装：YES
技术：CMOS电信集成电路类型：RF AND BASEBAND CIRCUIT
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmBase Number Matches：1

MAX5865E/D 数据手册

 浏览型号MAX5865E/D的Datasheet PDF文件第20页浏览型号MAX5865E/D的Datasheet PDF文件第21页浏览型号MAX5865E/D的Datasheet PDF文件第22页浏览型号MAX5865E/D的Datasheet PDF文件第24页浏览型号MAX5865E/D的Datasheet PDF文件第25页浏览型号MAX5865E/D的Datasheet PDF文件第26页 
Ultra-Low-Power, High-Dynamic-  
Performance, 40Msps Analog Front End  
DAC Offset Error  
Offset error (Figure 12a) is the difference between the  
CLK  
ideal and actual offset point. The offset point is the out-  
put value when the digital input is midscale. This error  
affects all codes by the same amount and usually can  
be compensated by trimming.  
ANALOG  
INPUT  
ADC Gain Error  
Ideally, the ADC full-scale transition occurs at 1.5 LSB  
below full scale. The gain error is the amount of devia-  
tion between the measured transition point and the  
ideal transition point with the offset error removed.  
t
AD  
t
AJ  
SAMPLED  
DATA (T/H)  
ADC Dynamic Parameter Definitions  
HOLD  
TRACK  
TRACK  
T/H  
Aperture Jitter  
Figure 13 depicts the aperture jitter (t ), which is the  
AJ  
sample-to-sample variation in the aperture delay.  
Figure 13. T/H Aperture Timing  
Aperture Delay  
Total Harmonic Distortion (THD)  
THD is typically the ratio of the RMS sum of the first five  
harmonics of the input signal to the fundamental itself.  
This is expressed as:  
Aperture delay (t ) is the time defined between the  
AD  
rising edge of the sampling clock and the instant when  
an actual sample is taken (Figure 13).  
Signal-to-Noise Ratio (SNR)  
For a waveform perfectly reconstructed from digital  
samples, the theoretical maximum SNR is the ratio of  
the full-scale analog input (RMS value) to the RMS  
quantization error (residual error) and results directly  
from the ADC’s resolution (N bits):  
2
2
2
2
2
(V +V +V +V +V )  
2
3
4
5
6
THD = 20log  
V
1
where V is the fundamental amplitude and V –V are  
the amplitudes of the 2nd- through 6th-order harmonics.  
1
2
6
Third Harmonic Distortion (HD3)  
HD3 is defined as the ratio of the RMS value of the third  
harmonic component to the fundamental input signal.  
SNR(max) = 6.02dB x N + 1.76dB (in dB)  
In reality, there are other noise sources besides quanti-  
zation noise: thermal noise, reference noise, clock jitter,  
etc. SNR is computed by taking the ratio of the RMS  
signal to the RMS noise. RMS noise includes all spec-  
tral components to the Nyquist frequency excluding the  
fundamental, the first five harmonics, and the DC offset.  
Spurious-Free Dynamic Range (SFDR)  
SFDR is the ratio expressed in decibels of the RMS  
amplitude of the fundamental (maximum signal compo-  
nent) to the RMS value of the next-largest spurious  
component, excluding DC offset.  
Signal-to-Noise Plus Distortion (SINAD)  
SINAD is computed by taking the ratio of the RMS sig-  
nal to the RMS noise. RMS noise includes all spectral  
components to the Nyquist frequency excluding the  
fundamental and the DC offset.  
Intermodulation Distortion (IMD)  
IMD is the total power of the intermodulation products  
relative to the total input power when two tones, f and  
1
f , are present at the inputs. The intermodulation prod-  
2
ucts are (f  
f ), (2 ✕ f ), (2 ✕ f ), (2 ✕ f  
f ), (2 ✕ f  
2 2  
1
2
1
2
1
Effective Number of Bits (ENOB)  
ENOB specifies the dynamic performance of an ADC at a  
specific input frequency and sampling rate. An ideal  
ADC’s error consists of quantization noise only. ENOB for  
a full-scale sinusoidal input waveform is computed from:  
f ). The individual input tone levels are at -7dBFS.  
1
3rd-Order Intermodulation (IM3)  
IM3 is the power of the worst third-order intermodula-  
tion product relative to the input power of either input  
tone when two tones, f and f , are present at the  
1
2
inputs. The 3rd-order intermodulation products are (2 x  
f ), (2 ✕ f f ). The individual input tone levels are  
ENOB = (SINAD - 1. 76) / 6.02  
f
1
2
2
1
at -7dBFS.  
______________________________________________________________________________________ 23  
1...20212223242526

下载PDF

与MAX5865E/D相关器件

型号 品牌 描述 获取价格 数据表
MAX5865ETM MAXIM Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End

获取价格
MAX5865ETM+ MAXIM RF and Baseband Circuit, CMOS, 7 X 7 MM, 0.80 MM HEIGHT, TQFN-48

获取价格
MAX5865ETM+T MAXIM RF and Baseband Circuit, CMOS, 7 X 7 MM, 0.80 MM HEIGHT, TQFN-48

获取价格
MAX5865ETM-T MAXIM RF and Baseband Circuit, CMOS, 7 X 7 MM, 0.80 MM HEIGHT, TQFN-48

获取价格
MAX5865EVKIT MAXIM Evaluation Kit for the MAX5865

获取价格
MAX5866 MAXIM Ultra-Low-Power. High-Dynamic-Performance. 60Msps Analog Front End

获取价格

与MAX5865E/D相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证