Datasheet > MAX5871EXE+

MAX5871EXE+

更新时间： 2024-01-30 10:54:59

品牌	Logo	应用领域
美信 - MAXIM		转换器
页数	文件大小	规格书
108页	1411K
描述
D/A Converter,

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技术参数
数据手册

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MAX5871EXE+ 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	LFBGA, bga144,12X12,32	Reach Compliance Code：	unknown
Factory Lead Time：	19 weeks	风险等级：	2.42
最大模拟输出电压：	2.2 V	最小模拟输出电压：	1.4 V
转换器类型：	D/A CONVERTER	输入位码：	OFFSET BINARY
输入格式：	SERIAL	JESD-30 代码：	S-PBGA-B144
长度：	10 mm	位数：	16
功能数量：	1	端子数量：	144
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装等效代码：	bga144,12X12,32	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH	座面最大高度：	1.265 mm
最大压摆率：	345 mA	标称供电电压：	1 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	宽度：	10 mm
Base Number Matches：	1

MAX5871EXE+ 数据手册

EVALUATION KIT AVAILABLE

Click here for production status of speciﬁc part numbers.

MAX5871

16-Bit, 5.9Gsps Interpolating and

Modulating RF DAC with JESD204B Interface

General Description

Beneﬁts and Features

● Simplifies RF Design and Enables New Wireless

The MAX5871 high-performance interpolating and modu-

lating 16-bit 5.9Gsps RF DAC can directly synthesize

up to 600MHz of instantaneous bandwidth from DC to

frequencies greater than 2.8GHz. The device enables

multi-standard and multi-band transmitters in wireless

communications applications. The device meets spectral

mask requirements for a broad set of communication

standards including multicarrier GSM, UMTS, and LTE.

Communication Architectures

• Eliminates I/Q Imbalance and LO Feedthrough

• Enables Multi-Band RF Modulation

●

Direct RF Synthesis of 600MHz Bandwidth Up to 2.8GHz

• 5.898Gsps DAC Output Update Rate

• High-Performance 14-Bit RF DAC Core

• Digital Quadrature Modulator and NCO with

1Hz/10Hz/100Hz/1kHz/10kHz Resolution

• 5x/6x/6.67x/8x/10x/12x/13.33x/16x/20x/24x

Interpolation

The device integrates interpolation filters, a digital quadra-

ture modulator, a numerically controlled oscillator (NCO),

clock multiplying PLL+VCO and a 14-bit RF DAC core.

The user-configurable 5x, 6x, 6.67x, 8x, 10x, 12x, 13.33x,

16x, 20x or 24x, linear phase interpolation filters sim-

plify reconstruction filtering, while enhancing passband

dynamic performance, and reduce the input data band-

width required from an FPGA/ASIC. The NCO allows for

fully agile modulation of the input baseband signal for

direct RF synthesis.

• Integrated Clock Multiplying PLL+VCO

● Highly Flexible and Configurable

• 1, 2, or 4-Lane JESD204B Input Data Interface

▫ Subclass-0 and Subclass-1 Compliant

▫ Up to 10Gbps Per Lane

• Reference Clock for System Synchronization

• Multiple DAC Synchronization (Subclass-1)

• SPI Interface for Device Conﬁguration

The MAX5871 accepts 16-bit input data via a four-lane

JESD204B SerDes data input interface that is Subclass-0

and Subclass-1 compliant. The interface can be config-

ured for 1, 2, or 4 lanes and supports data rates up to

10Gbps per lane allowing flexibility to optimize the I/O

count and speed.

Applications

● Cellular Base-Station Transmitters

• 2.5G/3G - GSM/TDMA/CDMA/UMTS

• 4G LTE and WiMAX

● Multi-Standard and Multi-Band Transmitters

● Point-to-Point Microwave Links

● Wireless Backhaul

The MAX5871 clock input has a flexible clock interface

and accepts a differential sine-wave, or square-wave

input clock signal. A bypassable clock multiplying PLL

and VCO can be used to generate a high-frequency sam-

pling clock. The device outputs a divided reference clock

to ensure synchronization of the system clock and DAC

clock. In addition, multiple devices can be synchronized

using JESD204B Subclass-1.

Simpliﬁed Block Diagram

PLL_COMP VCOBYP

MAX5871

CLOCK

DISTRIBUTION

RCLKP

RCLKN

CLKP

CLKN

PLL

The MAX5871 uses a differential current-steering archi-

tecture and can produce a 0dBm full-scale output signal

level with a 50Ω load. Operating from 1.8V and 1.0V

power supplies, the device consumes 2.5W at 4.9Gsps.

The device is offered in a compact 144-pin, 10mm x

10mm, FCCSP package and is specified for the extended

industrial temperature range (-40°C to +85°C).

MOD

SYSREFP

SYSREFN

MUTE

14-BIT

5.9Gsps

RF DAC

OUTP

OUTN

DP[3:0]

DN[3:0]

JESD

204B

SYNC

SYNCNP

SYNCNN

SYNCOP

SYNCON

SYNC

INTB

REFERENCE

SYSTEM

QUADRATURE

NCO

SPI PORT

RESETB

Ordering Information appears at end of data sheet.

19-7462; Rev 1; 7/19

12 3 4 5 6 7...108

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