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MAX5865E/D PDF预览

MAX5865E/D

更新时间： 2024-02-01 03:58:12
品牌 Logo 应用领域
美信 - MAXIM 电信集成电路蜂窝电话电路电信电路
页数 文件大小 规格书
26页 2143K
描述
Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End

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MAX5865E/D 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFN
包装说明：7 X 7 MM, 0.80 MM HEIGHT, TQFN-48针数：48
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.12Is Samacsys：N
模拟输入最大值：1.5 V输入类型：DIFFERENTIAL
JESD-30 代码：S-XQCC-N48JESD-609代码：e0
长度：7 mm信道数量：2
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出：VOLTAGE输出代码：OFFSET BINARY
最大输出电压：3 V封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC48,.27SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.8,3.3 V
认证状态：Not Qualified分辨率：8 µm
座面最大高度：0.8 mm子类别：Codecs
标称供电电压：3 V表面贴装：YES
技术：CMOS电信集成电路类型：RF AND BASEBAND CIRCUIT
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmBase Number Matches：1

MAX5865E/D 数据手册

 浏览型号MAX5865E/D的Datasheet PDF文件第17页浏览型号MAX5865E/D的Datasheet PDF文件第18页浏览型号MAX5865E/D的Datasheet PDF文件第19页浏览型号MAX5865E/D的Datasheet PDF文件第21页浏览型号MAX5865E/D的Datasheet PDF文件第22页浏览型号MAX5865E/D的Datasheet PDF文件第23页 
Ultra-Low-Power, High-Dynamic-  
Performance, 40Msps Analog Front End  
Using Op-Amp Coupling  
ID+  
V
OUT  
Drive the MAX5865 ADCs with op amps when a balun  
transformer is not available. Figures 9 and 10 show the  
ADCs being driven by op amps for AC-coupled single-  
ended, and DC-coupled differential applications.  
Amplifiers such as the MAX4354/MAX4454 provide  
high speed, high bandwidth, low noise, and low distor-  
tion to maintain the input signal integrity. Figure 10 can  
also be used to interface with the DAC differential ana-  
log outputs to provide gain or buffering. The DAC dif-  
ferential analog outputs cannot be used in single-  
ended mode because of the internally generated  
1.4VDC common-mode level. Also, the DAC analog  
outputs are designed to drive a differential input stage  
with input impedance ≥70kΩ. If single-ended outputs  
are desired, use an amplifier to provide differential to  
single-ended conversion and select an amplifier with  
proper input common-mode voltage range.  
MAX5865  
ID-  
QD+  
V
OUT  
QD-  
Figure 8. Balun-Transformer Coupled Differential to Single-  
Ended Output Drive for DACs  
FDD and TDD Modes  
The MAX5865 can be used in diverse applications  
operating FDD or TDD modes. The MAX5865 operates  
in Xcvr mode for FDD applications such as WCDMA-  
3GPP (FDD) and 4G technologies. Also, the MAX5865  
can switch between Tx and Rx modes for TDD applica-  
tions like TD-SCDMA, WCDMA-3GPP (TDD),  
IEEE802.11a/b/g, and IEEE802.16.  
REFP  
1kΩ  
1kΩ  
R
ISO  
50Ω  
V
IN  
0.1µF  
INA+  
COM  
INA-  
C
IN  
22pF  
100Ω  
100Ω  
In FDD mode, the ADC and DAC operate simultaneously.  
The ADC bus and DAC bus are dedicated and must be  
connected in 18-bit parallel (8-bit ADC and 10-bit DAC)  
to the digital baseband processor. Select Xcvr mode  
through the 3-wire serial interface and use the conversion  
clock to latch data. In FDD mode, the MAX5865 uses  
REFN  
0.1µF  
R
ISO  
50Ω  
C
22pF  
IN  
75.6mW power at f  
= 40MHz. This is the total power  
CLK  
of the ADC and DAC operating simultaneously.  
REFP  
In TDD mode, the ADC and DAC operate independent-  
ly. The ADC and DAC bus are shared and can be con-  
nected together, forming a single 10-bit parallel bus to  
the digital baseband processor. Using the 3-wire serial  
interface, select between Rx mode to enable the ADC  
and Tx mode to enable the DAC. When operating in Rx  
mode, the DAC does not transmit because the core is  
disabled and in Tx mode, the ADC bus is tri-state. This  
eliminates any unwanted spurious emissions and pre-  
vents bus contention. In TDD mode, the MAX5865 uses  
MAX5865  
R
1kΩ  
ISO  
50Ω  
V
IN  
0.1µF  
INB+  
C
IN  
22pF  
100Ω  
100Ω  
1kΩ  
REFN  
0.1µF  
R
ISO  
50Ω  
63mW power in Rx mode at f  
DAC uses 38.4mW in Tx mode.  
= 40MHz, and the  
CLK  
INB-  
C
IN  
Figure 11 illustrates the MAX5865 working with the  
MAX2820 in TDD mode to provide a complete 802.11b  
radio front-end solution. Because the MAX5865 DAC has  
full differential analog outputs with a common-mode level  
of 1.4V, and the ADC has wide-input common-mode  
22pF  
Figure 9. Single-Ended Drive for ADCs  
20 ______________________________________________________________________________________  
1...17181920212223...26

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