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MAX20340EWL+ PDF预览

MAX20340EWL+

更新时间: 2024-10-28 20:07:19
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
35页 1729K
描述
Power Supply Support Circuit,

MAX20340EWL+ 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:,Reach Compliance Code:unknown
风险等级:1.52可调阈值:YES
模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUITJESD-30 代码:S-PBGA-B9
信道数量:1功能数量:1
端子数量:9最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装形状:SQUARE最大供电电流 (Isup):0.05 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3.4 V
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:BALL
端子位置:BOTTOMBase Number Matches:1

MAX20340EWL+ 数据手册

 浏览型号MAX20340EWL+的Datasheet PDF文件第2页浏览型号MAX20340EWL+的Datasheet PDF文件第3页浏览型号MAX20340EWL+的Datasheet PDF文件第4页浏览型号MAX20340EWL+的Datasheet PDF文件第6页浏览型号MAX20340EWL+的Datasheet PDF文件第7页浏览型号MAX20340EWL+的Datasheet PDF文件第8页 
MAX20340  
Bidirectional DC Powerline  
Communication Management IC  
(T = -40C to +85C, V = +3.4V to +5.5V, unless otherwise noted. Typical values are at TA = +25°C. (Note 1))  
A
CC  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
RSEL Config 6  
Threshold  
R
R
R
23.491  
24.9  
26.662  
kΩ  
SEL6  
SEL7  
SEL8  
RSEL Config 7  
Threshold  
30.046  
37.631  
31.6  
33.599  
kΩ  
kΩ  
RSEL Config 8  
Threshold  
POWERLINE COMMUNICATION  
2
Time Unit  
t
I C programmable  
PLC_SINK = 00  
PLC_SINK = 01  
PLC_SINK = 10  
PLC_SINK = 11  
24  
s  
UNIT  
200  
244  
288  
355  
PLC Current Sink  
I
mA  
PLC_SNK  
DYNAMIC  
From BAT (master) or PLC (slave) above  
POR threshold to RSEL_DONEi (0x07[4])  
bit set  
Device Identification  
Ready Time  
t
3
3.48  
+16  
ms  
%
ID  
General Timing  
Accuracy  
t
-16  
ACC  
DIGITAL SIGNALS (SDA, SCL,  
Input Logic-High  
,
)
V
1.4  
-1  
V
V
IH  
Input Logic-Low  
V
0.4  
+1  
IL  
Input Leakage Current  
I
, SCL  
μA  
IN_LKG  
Output Logic-High  
Leakage Current (Open  
Drain)  
I
V
= 5.5V, SDA and  
1
μA  
OH_LKG  
IO  
Output Logic-Low  
V
I
= 20mA  
0.4  
V
OL  
SINK  
2
I C TIMING (Figure 4)  
I2C Serial Clock  
Frequency  
f
400  
kHz  
µs  
SCL  
Bus Free Time Between  
a STOP and START  
Condition  
t
1.3  
BUF  
START Condition  
(Repeated) Hold Time  
t
0.6  
1.3  
0.6  
µs  
µs  
µs  
HD:STA  
Low Period of SCL  
Clock  
t
LOW  
High Period of SCL  
Clock  
t
HIGH  
Setup Time for a  
Repeated START  
Condition  
t
0.6  
µs  
SU:STA  
www.maximintegrated.com  
Maxim Integrated | 5  

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