Datasheet > MACH211SP-12

MACH211SP-12

更新时间： 2024-10-27 22:10:23

品牌	Logo	应用领域
超微 - AMD		可编程逻辑
页数	文件大小	规格书
37页	253K
描述
High-Density EE CMOS Programmable Logic

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数据手册

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MACH211SP-12 数据手册

FINAL

COM’L: -7.5/10/12/15/20

IND: -10/12/14/18/24

MACH211SP-7/10/12/15/20

High-Density EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

■ JTAG-Compatible, 5-V in-system programming

■ Peripheral Component Interconnect (PCI)

compliant (-7/-10)

■ 44 Pins

■ Programmable power-down mode

■ 32 Outputs

■ 64 Macrocells

■ 7.5 ns t Commercial

10 ns t Industrial

■ 64 Flip-ﬂops; 2 clock choices

■ 4 “PAL26V16” blocks with buried macrocells

■ Improved routing over the MACH210

■ 133 MHz f

CNT

■ 34 Bus-Friendly™ Inputs and I/Os

IN-SYSTEM PROGRAMMING

In-system programming allows the MACH211SP to be

programmed while soldered onto a system board. Pro-

gramming the MACH211SP in-system yields numer-

ous beneﬁts at all stages of development: prototyping,

manufacturing, and in the ﬁeld. Since insertion into a

programmer isn’t needed, multiple handling steps and

the resulting bent leads are eliminated.The design can

be modiﬁed in-system for design changes and debug-

ging while prototyping, programming boards in produc-

tion, and ﬁeld upgrades.

The MACH211SP offers advantages not available in

other CPLD architectures with in-system programming.

MACH devices have extensive routing resources for

pin-out retention; design changes resulting in pin-out

changes for other CPLDs cancel the advantages of

in-system programming. The MACH211SP can be em-

ployed in any JTAG (IEEE 1149.1) compliant chain.

GENERAL DESCRIPTION

The MACH211SP is a member of AMD’s EE CMOS

Performance Plus MACH 2 device family. This device

has approximately six times the logic macrocell capa-

bility of the popular PAL22V10 without loss of speed.

programmable polarity. If a registered conﬁguration is

chosen, the register can be conﬁgured as D-type or

T-type to help reduce the number of product terms.The

by the software. All output macrocells can be con-

nected to an I/O cell. If a buried macrocell is desired,

the internal feedback path from the macrocell can be

used, which frees up the I/O pin for use as an input.

The MACH211SP consists of four PAL blocks inter-

connected by a programmable switch matrix. The four

PAL blocks are essentially “PAL26V16” structures com-

plete with product-term arrays and programmable

macrocells, which can be programmed as high speed

or low power, and buried macrocells. The switch matrix

connects the PAL blocks to each other and to all input

pins, providing a high degree of connectivity between

the fully-connected PAL blocks. This allows designs to

be placed and routed efﬁciently.

The MACH211SP has dedicated buried macrocells

which, in addition to the capabilities of the output

macrocell, also provide input registers or latches for

use in synchronizing signals and reducing setup time

requirements.

The MACH211SP is an enhanced version of the

MACH211, adding the JTAG-compatible in-system pro-

gramming feature.

The MACH211SP has two kinds of macrocell: output

and buried. The MACH211SP output macrocell pro-

vides registered, latched, or combinatorial outputs with

Publication# 20405 Rev: B Amendment/0

Issue Date: February 1996

12 3 4 5 6 7...37

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与MACH211SP-12相关器件

型号	品牌	获取价格	描述	数据表
MACH211SP-12JC	LATTICE	获取价格	High-Performance EE CMOS Programmable Logic
MACH211SP-12JC	AMD	获取价格	High-Density EE CMOS Programmable Logic
MACH211SP-12JC/1	LATTICE	获取价格	EE PLD, 12ns, CMOS, PQCC44,
MACH211SP-12JI	LATTICE	获取价格	High-Performance EE CMOS Programmable Logic
MACH211SP-12JI/1	LATTICE	获取价格	EE PLD, 14ns, CMOS, PQCC44,
MACH211SP-12VC	AMD	获取价格	High-Density EE CMOS Programmable Logic
MACH211SP-12VC	LATTICE	获取价格	High-Performance EE CMOS Programmable Logic
MACH211SP-12VC/1	LATTICE	获取价格	EE PLD, 12ns, CMOS, PQFP44,
MACH211SP-12VI/1	LATTICE	获取价格	EE PLD, 14ns, CMOS, PQFP44,
MACH211SP-14	ETC	获取价格	High-Performance EE CMOS In-System Programmable Logic

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