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M74HCT373M1R PDF预览

M74HCT373M1R

更新时间: 2024-11-22 23:01:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
13页 271K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HCT373 NON INVERTING - HCT533 INVERTING

M74HCT373M1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.27
系列:HCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):150 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:45 ns传播延迟(tpd):56 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mm

M74HCT373M1R 数据手册

 浏览型号M74HCT373M1R的Datasheet PDF文件第2页浏览型号M74HCT373M1R的Datasheet PDF文件第3页浏览型号M74HCT373M1R的Datasheet PDF文件第4页浏览型号M74HCT373M1R的Datasheet PDF文件第5页浏览型号M74HCT373M1R的Datasheet PDF文件第6页浏览型号M74HCT373M1R的Datasheet PDF文件第7页 
M54/74HCT373  
M54/74HCT533  
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT  
HCT373 NON INVERTING - HCT533 INVERTING  
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HIGH SPEED  
PD = 17 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
COMPATIBLE WITH TTL OUTPUTS  
t
V
IH = 2V (MIN.) VIL = 0.8 V (MAX.)  
B1R  
(Plastic Package)  
F1R  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOL = IOH = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS373/533  
ORDER CODES :  
M54HCTXXXF1R  
M74HCTXXXB1R  
M74HCTXXXM1R  
M74HCTXXXC1R  
DESCRIPTION  
The M54/74HCT373 and M54HCT533 are high  
speed CMOS OCTAL LATCH WITH 3-STATE  
OUTPUTS fabricated with in silicon gate C2MOS  
technology.  
These ICs achive the high speed operation similar  
to equivalent LSTTL while maintaning the CMOS  
low power dissipation.  
These 8 bit D-Type latches are controlled by a latch  
enable input (LE) and a output enable input (OE).  
While the LE input is held at a high level, the Q  
outputs will follow the data input precisely or  
inversely. When the LE is taken low, the Q outputs  
will be latched precisely or inversely at the logic level  
of D input data. While the OE input is at low level,  
the eight outputs will be in a normal logic state (high  
or low logic level) and while high level the outpts will  
be in a high impedance state. The application  
designer has a choise of combination of inverting  
and non inverting outputs. The three state output  
configuration and the wide choise of outline make  
bus organized system simple.  
These integrated circuits have input and output  
characteristics that are fully compatible with 54/74  
LSTTL logic families. M54/74HCT devices are  
designed to directly interface HSC2MOS systems  
with TTL and NMOS components. They are also  
plug in replacements for LSTTL devices giving a  
reduction of power consumption. All inputs are  
equipped with protection circuits against discharge  
and transient excess voltage.  
PIN CONNECTION (top view)  
HCT373  
HCT533  
HCT373  
HCT533  
October 1993  
1/13  

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