M74HCT374TTR

更新时间： 2024-11-23 05:10:55

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		触发器输出元件
页数	文件大小	规格书
11页	234K
描述
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING

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中文翻译

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数据手册

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M74HCT374TTR 数据手册

M74HCT374

OCTAL D-TYPE FLIP FLOP

WITH 3 STATE OUTPUT NON INVERTING

■

HIGH SPEED:

= 50 MHz (TYP.) at V = 4.5V

MAX

LOW POWER DISSIPATION:

= 4µA(MAX.) at T =25°C

COMPATIBLE WITH TTL OUTPUTS :

= 2V (MIN.) V = 0.8V (MAX)

DIP

SOP

TSSOP

BALANCED PROPAGATION DELAYS:

PLH

PHL

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 6mA (MIN)

ORDER CODES

PACKAGE

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 374

TUBE

T & R

DIP

SOP

M74HCT374B1R

M74HCT374M1R M74HCT374RM13TR

M74HCT374TTR

DESCRIPTION

TSSOP

The M74HCT374 is an high speed CMOS OCTAL

D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS

NON INVERTING fabricated with silicon gate

The output control does not affect the internal

operation of flip-flops; that is, the old data can be

retained or the new data can be entered even

while the outputs are off.

The M74HCT374 is designed to directly interface

HSC MOS systems with TTL and NMOS

C MOS technology.

This 8 bit D-TYPE FLIP FLOP is controlled by a

clock input (CK) and an output enable input (OE).

On the positive transition of the clock, the Q

outputs will be set to the logic state that were

setup at the D inputs.

components.

While the OE input is at low level, the eight outputs

will be in a normal logic state (high or low logic

level) and while OE is at high level the outputs will

be in a high impedance state.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

July 2001

1/11

12 3 4 5 6 7...11

中文翻译

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