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M74HC533TTR PDF预览

M74HC533TTR

更新时间: 2024-11-13 05:00:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
11页 262K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT INVERTING

M74HC533TTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.48系列:HC/UH
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
湿度敏感等级:3位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:38 ns
传播延迟(tpd):265 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

M74HC533TTR 数据手册

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M74HC533  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUT INVERTING  
HIGH SPEED:  
= 12ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
V
DIP  
SOP  
M74HC533B1R  
M74HC533M1R  
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 533  
M74HC533RM13TR  
M74HC533TTR  
TSSOP  
DESCRIPTION  
While the OE input is at low level, the eight outputs  
will be in a normal logic state (high or low logic  
level) and while high level the outputs will be in a  
high impedance state.  
The M74HC533 is an high speed CMOS OCTAL  
LATCH WITH 3-STATE OUTPUTS fabricated  
with silicon gate C MOS technology.  
2
This 8-BIT D-Type latches is controlled by a latch  
enable input (LE) and output enable input (OE).  
While the LE input is held at a high level, the Q  
outputs will follow the data input. When the LE is  
taken, the Q outputs will be latched at the logic  
level of D input data.  
The 3-State output configuration and the wide  
choice of outline make bus organized system  
simple.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

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