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M74HC51C1R PDF预览

M74HC51C1R

更新时间: 2024-11-12 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
9页 237K
描述
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE

M74HC51C1R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:PLASTIC, CC-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.82其他特性:ASYMMETRICAL I/P'S
系列:HC/UHJESD-30 代码:S-PQCC-J20
JESD-609代码:e3长度:8.9662 mm
负载电容(CL):50 pF逻辑集成电路类型:AND-OR-INVERT GATE
最大I(ol):0.004 A功能数量:2
输入次数:6端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:25 ns
传播延迟(tpd):25 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:4.57 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.9662 mmBase Number Matches:1

M74HC51C1R 数据手册

 浏览型号M74HC51C1R的Datasheet PDF文件第2页浏览型号M74HC51C1R的Datasheet PDF文件第3页浏览型号M74HC51C1R的Datasheet PDF文件第4页浏览型号M74HC51C1R的Datasheet PDF文件第5页浏览型号M74HC51C1R的Datasheet PDF文件第6页浏览型号M74HC51C1R的Datasheet PDF文件第7页 
M54HC51  
M74HC51  
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE  
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HIGH SPEED  
tPD = 10 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 1 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS51  
ORDER CODES :  
M54HC51F1R  
M74HC51B1R  
M74HC51M1R  
M74HC51C1R  
DESCRIPTION  
The M54/74HC51 is a high speed CMOS DUAL 2  
WIDE-2 INPUT AND/OR INVERT GATE fabricated  
in silicon gate C2MOS technology. It has the same  
high speed performance of LSTTL combined with  
true CMOS low power consumption. It contains a 2-  
WIDE 2-INPUT AND-OR-INVERT GATE and a 2-  
WIDE 3-INPUT AND-OR-INVERT GATE.  
PIN CONNECTIONS (top view)  
The internal circuit is composed of 3 stages (2-  
INPUT) or 5 stages (3-INPUT) including buffered  
output, which gives high noise immunity and a  
stableoutput.Allinputs are equipped withprotection  
circuits against static discharge and transient ex-  
cess voltage.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
December 1992  
1/9  

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