MITSUBISHI DIGITAL ASSP
M66242P/FP
4-CH 12-BIT PWM GENERATOR
FUNCTION
subsections t, each of which has this basic waveform. Among
them, those which are designated by the 4-bit-rate multiplier
are conditioned to have a “H” width that is longer by τ. The
lower 4 bits of PWM data are used to specify those subsec-
tions (tm). The waveform of other subsections remains un-
changed.
The PWM output waveform of each channel is controlled by
taking in PWM data from MCU or other device via serial data
input SIN.
Twelve-bit PWM data is input being divided between upper 8
bits (upper byte) and lower 4 bits.
The lower 4-bit data is combined with command data such as
channel designation and input as 8-bit data (lower byte).
The lower byte should be written first, and then the upper
byte. Even if only the upper byte is to be changed, rewrite
from the lower byte.
The PWM waveform changes according to the new setting
from the next cycle.
One cycle of PWM waveform (4096 divisions; 12-bit resolu-
tion) are divided into 16 (24) subsections t. Each subsection
consists of 256 (28; 8-bit resolution) minimum bits τ (=2/
fXIN**).
A PWM waveform (12-bit resolution) is a combination of two
types of waveforms which are different in “H” width, as de-
scribed above.
When output control input OC is “H”, the output of every
channel turns high-impedance from the next cycle.
When reset input R is “L”, the output of every channel turns
high-impedance as soon as the ongoing cycle is completed,
and PWM data of all channels is reset. If R input is changed
from “L” to “H”, the next cycle starts, however, the output of
the channels remains high-impedance.
To enable output, rewrite input data for each channel.
One subsection t consists of a 8-bit PWM waveform (basic
waveform). The “H” width of this waveform is determined ac-
cording to the upper 8 bits of PWM data. One cycle has 16
**)fXIN: Clock XIN repeat frequency
PIN DESCRIPTIONS
Pin
Name
Reset input
Input/Output
Input
Functions
R
“L”: All 4 channels put in high impedance state.
“L”: Communication with MCU becomes possible. WR, SIN and SCLK put in
enable state.
CS
Chip select input
Write control input
Input
Input
“L”: Serial data written.
“L”-to-“H” edge: Written data stored in upper or lower byte.
WR
SIN
Serial data input
Input
Input
Inputs 8-bit serial data from MCU synchronously with clock pulses.
Inputs sync clock pulses for 8-bit serial data writing.
“H”: All 4 channels put in high-impedance state.
SCLK
OC
Write clock input
Output control input
PWM outputs 1 thru 4
Input
PWM1~PWM4
Output
Outputs PWM waveform. (CMOS 3-state output)
Inputs/outputs signals generated by clock signal generation circuit. Oscillation
frequency is determined by connecting ceramic or quartz resonator between
XIN and XOUT. The frequency of internal clock (PWM timing clock) signals is
the 1/2 divider of the frequency input from clock input XIN. When external
clock signals are used, connect clock generator to XIN pin and leave XOUT
open.
XIN
Clock input
Input
XOUT
Clock output
Output
2