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M65617SP PDF预览

M65617SP

更新时间: 2024-02-19 23:38:34
品牌 Logo 应用领域
三菱 - MITSUBISHI 消费电路商用集成电路光电二极管
页数 文件大小 规格书
15页 77K
描述
PICTURE-IN-PICTURE SIGNAL PROCESSING

M65617SP 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:SDIP, SDIP52,.6
针数:52Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PDIP-T52JESD-609代码:e0
长度:45.85 mm功能数量:1
端子数量:52最高工作温度:75 °C
最低工作温度:-10 °C封装主体材料:PLASTIC/EPOXY
封装代码:SDIP封装等效代码:SDIP52,.6
封装形状:RECTANGULAR封装形式:IN-LINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:5.5 mm
子类别:Superimposer ICs最大压摆率:140 mA
最大供电电压 (Vsup):3.5 V最小供电电压 (Vsup):3.1 V
表面贴装:NO温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:1.778 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15.24 mm
Base Number Matches:1

M65617SP 数据手册

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MITSUBISHI ICs (TV)  
M65617SP  
PICTURE-IN-PICTURE SIGNAL PROCESSING  
SERIAL REGISTER INFORMATION (cont.)  
Sub-  
address  
Reference  
setting  
Bit No.  
Register name  
Function  
0
1
2
3
4
1
1
1
1
1
dft-bl  
Register 10h<7:0>, 11h<3.0>default gate; [1 setting]  
dft-misc  
dft-sg  
Register 11h<7:4>default gate; [1 setting]  
Register 13h<7:0>, 14h<6>, 17h<7:6>default gate; [1 setting]  
Register 19h<7:0>default gate; [1 setting]  
dft-syncbst  
dft-clevel  
Register 12h<7:0>default gate; [1 setting]  
1Bh  
Signal selection at 29 pin output mode; fsc/4fsc [0/1] [0 setting]  
Operated when adjusting oscillation frequency  
5
6
0
pin29osel  
pin29oe  
29 pin output mode authorization input/output [0/1] [Normally 0 setting]  
Operated when adjusting oscillation frequency  
0
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
dft-clr  
Register 16h<7:0>default gate; [1 setting]  
imag (0)  
imag (1)  
For testing  
imag (2)  
imag (3)  
1Ch  
read  
iphase (0)  
iphase (1)  
iphase (2)  
iphase (3)  
iphase (4)  
iphase (5)  
iphase (6)  
iphase (7)  
iphase (8)  
for test  
For testing  
1Dh  
read  
For testing  
for test  
0 or 1  
0 or 1  
0 or 1  
0 or 1  
0 or 1  
0 or 1  
0 or 1  
rdof  
Simplified verification of main input loss; input unavailable/available [1/0]  
clamp-offset (0)  
clamp-offset (1)  
clamp-offset (2)  
clamp-offset (3)  
clamp-offset (4)  
clamp-offset (5)  
for test  
Clamping level information; for verification of internal operation information  
Values are shown that are in proportion and corresponding to the depth of sub-  
input information sync.  
1Eh  
read  
For testing  
0 or 1  
0 or 1  
0 or 1  
0 or 1  
0 or 1  
0 or 1  
0 or 1  
0 or 1  
wdof  
Simplified verification of sub-input loss; input unavailable/available [1/0]  
c-dac-ctrl (0)  
c-dac-ctrl (1)  
c-dac-ctrl (2)  
c-dac-ctrl (3)  
c-dac-ctrl (4)  
c-dac-ctrl (5)  
c-dac-ctrl (6)  
bw  
Level tracking information; for verification of internal operation information  
Values are shown that are in proportion and corresponding to main input burst  
amplitude  
1Fh  
read  
Unlock information; for verification of internal operation information  
10  

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