MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
APPLICATION
NTSC, PAL-M, PAL-N color TV
The M65665SP/FP is a PIP (Picture in Picture) signal
processing LSI, whose sub-picture input is composite
signal or component signals(Y/C or Y/U/V) for NTSC,
PAL-M, and PAL-N. The built-in field memory (168k-bit
RAM) , V-chip data slicer and analog circuitries lead the
high quality PIP sy stem low cost and small size.
RECOMMENDED OPERATING CONDITIONS
Supply v oltage range ------------------------ 3.2 ~ 3.5 V
Operating frequency
----------------------- 14.32 MHz
Operating temperature ------------------------ 0 ~ 70 deg.
Input v oltage (CMOS interface) "H" ----- VDD x 0.7 ~ VDD V
"L" -----
0 ~ VDD x 0.3 V
Output current ( output buf f er ) ------------ 4 mA ( MAX )
Output load capacitance ---------------------- 20 pF ( MAX ) *1
Circuit current -----------------------------------
FEATURES
-
mA
* Internal V-chip data slicer (for sub-picture)
* Vertical f ilter for sub-picture ( Y signal )
* Base band comb filter (2 Line)
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS pins.
*1 : Include pin capacitance ( 7 pF )
* Single sub-picture ( selectable picture size : 1/9 , 1/16 )
* Sub-picture processing specification ( 1/9 , 1/16 size) :
Quantization bits
Y, B-Y, R-Y : 7 bits
Horizontal sampling 229 pixels (Y), 57 pixels (B-Y, R-Y)
Vertical lines
69/ 52 lines
* Frame ( sub-picture ) on/off
* Built-in analog circuits :
Two 8-bit A/D converter (f or sub-picture signal)
Three 8-bit D/A conv erters (for Y, U and V of sub-picture)
Sy nc-tip-clamp, VCXO,OSD switch ... etc..
* IIC BUS control ( parallel/serial control) :
PIP on/off , Frame on/of f ( programmable luma lev el),
Sub-picture size ( 1/9, 1/16 ),
Block diagram & Application examples
Shown next pages
PIP position ( free position ), Picture f reeze ,
Y delay adjustment, Chroma lev el, Tint, Black lev el,
Contrast
...etc..
PIN CONFIGURATION (TOP VIEW)
42
1
SWM
Y(R)OUT
2
41
OSD_SEL
OSD_RIN
40
3
SDATA
AGndDA
4
39
SCLK
U(G)OUT
5
38
DVdd
OSD_GIN
6
37
DVss
VZ
7
36
V(B)OUT
BGPS
35
8
OSD_BIN
SCK
9
34
BGPM
VddDA
10
33
FSC
VD
11
32
TEST5
HD
12
31
ESTEN
AVss(vcxo)
13
30
X'tal(P-N)
SWMG
14
29
RESET
X'tal(P-M)
CSYNCS
AVdd(ad)
Vin(ad)
15
16
28
27
26
25
X'tal(NT)
BIAS
17
18
Filter
Uin(ad)
Vrb
AVdd(vcxo)
24
23
22
19
20
CVBSin(ad)
AVss(ad)
Yin(ad)
21
Vrt
Cin(ad)
Outline 42 Pin SDIP Package (M65665SP)
Outline 0.8mm pitch 42 Pin SOP Package (M65665FP)
1
MITSUBISHI
ELECTRIC