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M62333P PDF预览

M62333P

更新时间: 2024-11-11 05:47:19
品牌 Logo 应用领域
瑞萨 - RENESAS 转换器数模转换器缓冲放大器光电二极管
页数 文件大小 规格书
10页 128K
描述
8-bit 3ch I2C BUS D/A Converter with Buffer Amplifiers

M62333P 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP8,.3针数:8
Reach Compliance Code:compliant风险等级:5.68
Is Samacsys:N最大模拟输出电压:5.4 V
最小模拟输出电压:0.1 V转换器类型:D/A CONVERTER
输入位码:BINARY输入格式:SERIAL
JESD-30 代码:R-PDIP-T8长度:8.9 mm
最大线性误差 (EL):0.5859%位数:8
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
认证状态:Not Qualified座面最大高度:4.5 mm
子类别:Other Converters最大压摆率:2.7 mA
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

M62333P 数据手册

 浏览型号M62333P的Datasheet PDF文件第2页浏览型号M62333P的Datasheet PDF文件第3页浏览型号M62333P的Datasheet PDF文件第4页浏览型号M62333P的Datasheet PDF文件第5页浏览型号M62333P的Datasheet PDF文件第6页浏览型号M62333P的Datasheet PDF文件第7页 
M62333P/FP, M62338P/FP  
8-bit 3ch I2C BUS D/A Converter with Buffer Amplifiers  
REJ03D0865-0300  
Rev.3.00  
Jun 15, 2007  
Description  
The M62333/M62338 is an integrated circuit semiconductor of CMOS structure with 3 channels of built in D/A  
converters with output buffer operational amplifiers.  
The input is 2-wires serial method is used for the transfer format of digital data to allow connection with a  
microcomputer with minimum wiring.  
The output buffer operational amplifier employs AB class output circuit with sync and source drive capacity of 1.0 mA  
or more, and it operates in the whole voltage range from VCC to ground.  
The M62333 and the M62338 differ only in their slave address.  
Features  
Digital data transfer format: I2C BUS serial data method  
Output buffer operational amplifier: It operates in the whole voltage range from VCC to ground.  
High output current drive capacity: ±1.0 mA over  
Application  
Conversion from digital data to analog control data for home-use and industrial equipment.  
Signal gain control or automatic adjustment of Display-monitor or CTV.  
Block Diagram  
VCC  
8
SCL  
7
SDA  
6
GND  
5
I2C BUS transceiver  
Power on  
reset  
Channel  
decoder  
8
8-bit latch  
8-bit latch  
8-bit latch  
8-bit upper  
segment R-2R  
8-bit upper  
segment R-2R  
8-bit upper  
segment R-2R  
+
+
+ −  
1
2
3
AO1  
AO2  
AO3  
REJ03D0865-0300 Rev.3.00 Jun 15, 2007  
Page 1 of 9  

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