Datasheet > M5M5V5636UG-16

M5M5V5636UG-16

更新时间： 2024-02-09 20:38:33

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
25页	903K
描述
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

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中文翻译

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技术参数
数据手册

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M5M5V5636UG-16 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	针数：	165
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.87
最长访问时间：	3.8 ns	最大时钟频率 (fCLK)：	167 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
内存密度：	18874368 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	端子数量：	165
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	电源：	2.5/3.3 V
认证状态：	Not Qualified	最大待机电流：	0.03 A
最小待机电流：	2.38 V	子类别：	SRAMs
最大压摆率：	0.38 mA	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

M5M5V5636UG-16 数据手册

Renesas LSIs

M5M5V5636UG – 16

18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

PACKAGE

DESCRIPTION

165(11x15) bump BGA

Body Size (13mm x 15mm)

Bump Pitch 1.0mm

The M5M5V5636UG is a family of 18M bit synchronous

SRAMs organized as 524288-words by 36-bit. It is designed to

eliminate dead bus cycles when turning the bus around between

reads and writes, or writes and reads. Renesas's SRAMs are

fabricated with high performance, low power CMOS technology,

providing greater reliability. M5M5V5636UG operates on 3.3V

power/ 2.5V I/O supply or a single 3.3V power supply and are

3.3V CMOS compatible.

APPLICATION

High-end networking products that require high bandwidth, such

as switches and routers.

The M5M5V5636UG also operates on a single 2.5V power

supply and is also 2.5V CMOS compatible. Therefore the

M5M5V5636UG can replace the M5M5T5636UG.

FUNCTION

Synchronous circuitry allows for precise cycle control

triggered by a positive edge clock transition.

The M5M5V5636UG-16 operates at 167MHz or 133MHz and is

guaranteed both AC DC electrical characteristics of 167MHz and

those of 133MHz.

Synchronous signals include : all Addresses, all Data Inputs,

all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),

Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,

BWd#) and Read/Write (W#). Write operations are controlled by

the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)

inputs. All writes are conducted with on-chip synchronous

self-timed write circuitry.

Asynchronous inputs include Output Enable (G#), Clock (CLK)

and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the

SRAM in the power-down state.The Linear Burst order (LBO#) is

DC operated pin. LBO# pin will allow the choice of either an

interleaved burst, or a linear burst.

FEATURES

• Fully registered inputs and outputs for pipelined operation

• Fast clock speed: 167 and 133 MHz

• Fast access time: 3.8 and 4.2 ns

• Single 3.3V -5% and +5% power supply VDD

• Separate VDDQ for 3.3V or 2.5V I/O

• Single 2.5V -5% and +5% power supply VDD

• Individual byte write (BWa# - BWd#) controls may be tied

LOW

All read, write and deselect cycles are initiated by the ADV

LOW input. Subsequent burst address can be internally

generated as controlled by the ADV HIGH input.

• Single Read/Write control pin (W#)

• CKE# pin to enable clock and suspend operations

• Internally self-timed, registers outputs eliminate the need

to control G#

• Snooze mode (ZZ) for power down

• Linear or Interleaved Burst Modes

• Three chip enables for simple depth expansion

• JTAG boundary scan support

PART NAME TABLE

M5M5V5636UG-16

Active Current

(max.)

Standby Current

(max.)

Operate frequency

167MHz

Access

3.8ns

4.2ns

Cycle

6.0ns

7.5ns

380mA

350mA

30mA

133MHz

1/25

M5M5V5636UG-16 REV.2.0

12 3 4 5 6 7...25

中文翻译

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与M5M5V5636UG-16相关器件

型号	品牌	获取价格	描述	数据表
M5M5V5636UG-20	RENESAS	获取价格	512KX36 STANDARD SRAM, 3.2ns, PBGA165, 13 X 15 MM, 1.0 MM PITCH, BGA-165
M5M5V5A36GP	RENESAS	获取价格	18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
M5M5V5A36GP_1	RENESAS	获取价格	18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
M5M5V5A36GP-75	RENESAS	获取价格	18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
M5M5V5A36GP-75#A0	RENESAS	获取价格	IC,SYNC SRAM,512KX36,CMOS,QFP,100PIN,PLASTIC
M5M5V5A36GP-85	RENESAS	获取价格	18874368-BIT(524288-WORD BY 36-BIT) Flow-Through NETWORK SRAM
M5M5V5A36GP-85#A0	RENESAS	获取价格	Network Search Engine, LQFP, /Embossed Tape
M5M5V64R16CJ-10	MITSUBISHI	获取价格	Standard SRAM, 128KX8, 10ns, CMOS, PDSO44, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-44
M5M5V64R16CJ-10T	MITSUBISHI	获取价格	Standard SRAM, 128KX8, 10ns, CMOS, PDSO44, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-44
M5M5V64R16CJ-12	MITSUBISHI	获取价格	Standard SRAM, 128KX8, 12ns, CMOS, PDSO44, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-44

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