MITSUBISHI LSIs
MITSUBISHI LSIs
M5M44260CJ,TP-5,-6,-7,
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
-5S,-6S,-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
This is a family of 262144-word by 16-bit dynamic RAMs,
fabricated with the high performance CMOS process, and is ideal
for memory systems where high speed, low power dissipation, and
low costs are essential.
The use of double-layer metalization process technology and a
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is small enough for
battery back-up application.
VSS(0V)
(5V)VCC
DQ1
40
39
38
1
2
DQ16
DQ15
DQ2
3
4
5
DQ3
DQ4
37 DQ14
36
DQ13
(5V)VCC
DQ5
35 VSS(0V)
34 DQ12
6
7
This device has 2CAS and 1W terminals with a refresh cycle of
512 cycles every 8.2ms.
DQ6
DQ11
32 DQ10
DQ9
30 NC
33
8
DQ7
9
FEATURES
31
DQ8
10
11
Power
dissipa-
tion
Address
access
OE
RAS
access access
time time
(max.ns) (max.ns)
CAS
Cycle
time
(min.ns)
access
NC
Type name
time
time
(max.ns)
(typ.mW)
(max.ns)
NC
29
28
LCAS
UCAS
OE
12
13
14
M5M44260CXX-5,-5S
M5M44260CXX-6,-6S
M5M44260CXX-7,-7S
XX=J,TP
50
60
70
13
15
20
25
30
35
13
15
20
90
110
130
625
550
475
W
RAS
NC
27
26
25
24
23
22
21
15
16
A8
A7
A0
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
CMOS Input level
CMOS Input level
Operating power dissipation
M5M44260Cxx-5,-5S
M5M44260Cxx-6,-6S
M5M44260Cxx-7,-7S
Self refresh capability *
Self refresh current
Extended refresh capability
Extended refresh current
Fast-page mode (512-column random access), Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, LCAS / UCAS and OE to control output buffer
impedance
512 refresh cycles every 8.2ms (A0~A8)
512 refresh cycles every 128ms (A0~A8) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S
: option) only
17
18
A6
A1
A2
A5
5.5mW (Max)
550µW (Max) *
19
20
A3
A4
VSS(0V)
(5V)VCC
688mW (Max)
605mW (Max)
523mW (Max)
Outline 40P0K (400mil SOJ)
150µA (Max)
150µA (Max)
(5V)VCC
1
2
44 VSS(0V)
43
DQ1
DQ2
DQ16
42
3
4
DQ15
41
40
39
DQ14
DQ13
DQ3
DQ4
5
6
(5V)VCC
DQ5
VSS(0V)
DQ12
7
8
9
38
DQ11
DQ10
DQ9
DQ6
37
36
DQ7
DQ8 10
35
APPLICATION
Microcomputer memory, Refresh memory for CRT
NC
13
32
31
30
NC
14
15
16
17
18
19
20
21
22
NC
W
LCAS
PIN DESCRIPTION
UCAS
OE
Pin name
A0~A8
Function
Address inputs
29
28
RAS
NC
A0
A8
DQ1~DQ16
RAS
Data inputs / outputs
27 A7
Row address strobe input
26
25
24
23
A6
A1
A2
Lower byte control
column address strobe input
LCAS
A5
A4
Upper byte control
A3
UCAS
W
column address strobe input
VSS(0V)
(5V)VCC
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
OE
Outline 44P3W-R (400mil TSOP Nomal Bend)
VCC
VSS
NC: NO CONNECTION
1
M5M44260CJ,TP-5,-5S : Under development