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M54HCT10F1R PDF预览

M54HCT10F1R

更新时间: 2024-09-26 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
9页 234K
描述
TRIPLE 3-INPUT NAND GATE

M54HCT10F1R 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.77系列:HCT
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A功能数量:3
输入次数:3端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:33 ns
传播延迟(tpd):33 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

M54HCT10F1R 数据手册

 浏览型号M54HCT10F1R的Datasheet PDF文件第2页浏览型号M54HCT10F1R的Datasheet PDF文件第3页浏览型号M54HCT10F1R的Datasheet PDF文件第4页浏览型号M54HCT10F1R的Datasheet PDF文件第5页浏览型号M54HCT10F1R的Datasheet PDF文件第6页浏览型号M54HCT10F1R的Datasheet PDF文件第7页 
M54HCT10  
M74HCT10  
TRIPLE 3-INPUT NAND GATE  
.
.
.
.
.
.
.
HIGH SPEED  
tPD = 11 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 1 µA (MAX.) AT TA = 25 °C  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2V (MIN.) VIL = 0.8V (MAX)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
PIN AND FUNCTION COMPATIBLE WITH  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
54/74LS10  
ORDER CODES :  
DESCRIPTION  
M54HCT10F1R  
M74HCT10M1R  
M74HCT10B1R  
M74HCT10C1R  
The M54/74HCT10 is a high speed CMOS TRIPLE  
3-INPUT NAND GATE fabricated with silicon gate  
C2MOS technology. It has the same highspeed per-  
formance of LSTTL combined with true CMOS low  
power consumption. The internal circuit is com-  
posed of 3 stages including buffer output, which en-  
ables high noise immunity and stable output. All  
inputs are equipped with protection circuits against  
static discharge and transient excess voltage.  
PIN CONNECTIONS (top view)  
This integrated circuit has input and output charac-  
teristics that are fully compatible with 54/74 LSTTL  
logic families. M54/74HCT devices are designed to  
directly interface HSC2MOS systems with TTL and  
NMOS components. They are also plug in replace-  
ments for LSTTL devices giving a reduction of  
power consumption.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
February 1993  
1/9  

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