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M54HCT125F1R PDF预览

M54HCT125F1R

更新时间: 2024-09-27 03:53:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
10页 254K
描述
QUAD BUS BUFFERS 3-STATE

M54HCT125F1R 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:CERAMIC, DIP-14针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.5Is Samacsys:N
控制类型:ENABLE LOW系列:HCT
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
负载电容(CL):150 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:32 ns传播延迟(tpd):41 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

M54HCT125F1R 数据手册

 浏览型号M54HCT125F1R的Datasheet PDF文件第2页浏览型号M54HCT125F1R的Datasheet PDF文件第3页浏览型号M54HCT125F1R的Datasheet PDF文件第4页浏览型号M54HCT125F1R的Datasheet PDF文件第5页浏览型号M54HCT125F1R的Datasheet PDF文件第6页浏览型号M54HCT125F1R的Datasheet PDF文件第7页 
M54/74HCT125  
M54/74HCT126  
QUAD BUS BUFFERS (3-STATE)  
.
.
.
.
.
.
.
HIGH SPEED  
tPD = 12 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT 25 °C  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
SYMMETRICAL OUTPUT IMPEDANCE  
IOL = IOH = 6 mA (MIN.)  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2V (MIN.) VIL = 0.8V (MAX)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS125/126  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HCTXXXF1R  
M74HCTXXXB1R  
M74HCTXXXM1R  
M74HCTXXXC1R  
DESCRIPTION  
The M54/74HCT125/126 are high speed CMOS  
QUAD BUS BUFFER (3-STATE) FABRICATED IN  
SILICON GATE C2MOS technology. They have the  
same high speed performance ofLSTTL combined  
with true CMOS low power consumption. These de-  
vices require the same 3-STATE control input G to  
be takenhigh to make the output go into the high im-  
pedance state.This integrated circuit has input and  
output characteristics that are fully compatible with  
54/74 LSTTL logic families. M54/74HCT devices  
are designed to directly interface HSC2MOS sys-  
tems with TTL and NMOS components. They are  
also plug in replacements for LSTTL devices giving  
a reduction of power consumption. All inputs are  
equipped with protection circuits against static dis-  
charge and transient excess voltage.  
PIN CONNECTIONS (top view)  
HCT125  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
HCT126  
NC =  
No Internal  
Connection  
October 1993  
1/10  

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