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M54HCT164F1R PDF预览

M54HCT164F1R

更新时间： 2024-09-26 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
12页 255K
描述
8 BIT SIPO SHIFT REGISTER

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中文翻译

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M54HCT164F1R 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP14,.3针数：14
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.32Is Samacsys：N
计数方向：RIGHT系列：HCT
JESD-30 代码：R-GDIP-T14JESD-609代码：e0
负载电容（CL）：50 pF逻辑集成电路类型：SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup：20000000 Hz位数：8
功能数量：1端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP14,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
传播延迟（tpd）：54 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Shift Registers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：20 MHz
Base Number Matches：1

M54HCT164F1R 数据手册

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M54HCT164  
M74HCT164  
8 BIT SIPO SHIFT REGISTER  
.
.
.
.
.
.
.
.
HIGH SPEED  
PD = 20 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL = 4 mA (MIN.)  
SYMMETRICAL OUTPUT IMPEDANCE  
IOL = IOH = 4 mA (MIN)  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2V (MIN.) VIL = 0.8V (MAX)  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS164  
t
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HCT164F1R  
M74HCT164B1R  
M74HCT164M1R  
M74HCT164C1R  
DESCRIPTION  
The M54/74HCT164 is a high speed CMOS 8 BIT  
SIPO SHIFT REGISTER fabricated in silicon gate  
C2MOS technology. It has the same highspeed per-  
formance of LSTTL combined with true CMOS low  
power consumption.  
PIN CONNECTIONS (top view)  
The HCT164 is an 8 bit shift register with serial data  
entry and an output from each of the eight stages.  
Data is entered serially through one of two inputs (A  
or B), either of these inputs can beused asan active  
high enable for data entry through the other input.  
An unused input must be high, or both inputs con-  
nected together. Each low-to-high transition on the  
clock input shifts data one place to the right and  
entersintoQA, thelogic NAND of the twodata inputs  
(A • B), the data that existed before the rising clock  
edge. A low level on the clear input overrides all  
other inputs and clearsthe register asynchronously,  
forcing all Q outputs low.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
This integrated circuit has input and output charac-  
teristics that are fully compatible with 54/74 LSTTL  
logic families. M54/74HCT devices are designed to  
directly interface HSC2MOS systems with TTL and  
NMOS components. They are also plug in replace-  
ments for LSTTL devices giving a reduction of  
power consumption.  
NC =  
No Internal  
Connection  
February 1993  
1/12  
1234567...12

中文翻译

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