M54HCT138F1

更新时间： 2024-09-27 13:10:07

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
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数据手册

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M54HCT138F1 数据手册

M54HCT138

M74HCT138

3 TO 8 LINE DECODER (INVERTING)

HIGH SPEED

_PD= 16 ns (TYP.) at V_CC= 5 V

LOW POWER DISSIPATION

_CC= 4 µA AT T_A= 25 °C

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

SYMMETRICAL OUTPUT IMPEDANCE

|I_OH| = I_OL

COMPATIBLE WITH TTL OUTPUTS

V_IH= 2V (MIN.) V_IL= 0.8V (MAX)

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS138

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

DESCRIPTION

M54HCT138F1R

M74HCT138M1R

The M54/74HC138 is a high speed CMOS 3 TO 8

LINE DECODER fabricated in silicon gate C²MOS

technology. It has the same high speed perform-

ance of LSTTL combinedwithtrue CMOSlowpower

consumption. If the device is enabled, 3 binary se-

lect inputs (A, B and C) determine which one of the

outputs will go low. If enable input G1 is held low or

either G2A or G2B is held high, the decoding func-

tion is inhibited and all the 8 outputs go high. Three

enable inputs are provided toease cascade connec-

tion and application of address decoders for mem-

ory systems. All inputs are equipped with protection

circuits against static discharge and tran- sient ex-

cess voltage.This integrated circuit has input and

output characteristics that are fully compatible with

54/74 LSTTL logic families. M54/74HCT devices

are designed to directly interface HSC²MOS sys-

tems with TTL and NMOS components. They are

also plug in replacements for LSTTL devices giving

a reduction of power consumption.

M74HCT138B1R

M74HCT138C1R

PIN CONNECTIONS (top view)

INPUT AND OUTPUT EQUIVALENT CIRCUIT

NC =

No Internal

Connection

February 1993

1/10

12 3 4 5 6 7...10

中文翻译

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