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M5-256/120-15YC/1 PDF预览

M5-256/120-15YC/1

更新时间: 2024-10-30 04:52:43
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
42页 826K
描述
EE PLD, 15ns, 256-Cell, CMOS, PQFP160, PLASTIC, QFP-160

M5-256/120-15YC/1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, QFP-160
针数:160Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82其他特性:YES
最大时钟频率:55.6 MHz系统内可编程:YES
JESD-30 代码:S-PQFP-G160JESD-609代码:e0
JTAG BST:YES长度:28 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:120宏单元数:256
端子数量:160最高工作温度:70 °C
最低工作温度:组织:0 DEDICATED INPUTS, 120 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP160,1.2SQ
封装形状:SQUARE封装形式:FLATPACK
电源:5 V可编程逻辑类型:EE PLD
传播延迟:15 ns认证状态:Not Qualified
座面最大高度:4.1 mm子类别:Programmable Logic Devices
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:28 mmBase Number Matches:1

M5-256/120-15YC/1 数据手册

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MACH 5 CPLD Family  
Fifth Generation MACH Architecture  
FEATURES  
High logic densities and I/Os for increased logic integration  
— 128 to 512 macrocell densities  
— 68 to 256 I/Os  
Wide selection of density and I/O combinations to support most application needs  
— 6 macrocell density options  
— 7 I/O options  
— Up to 4 I/O options per macrocell density  
— Up to 5 density & I/O options for each package  
Performance features to fit system needs  
— 5.5 ns t Commercial, 7.5 ns t Industrial  
PD  
PD  
— 182 MHz f  
CNT  
— Four programmable power/speed settings per block  
Flexible architecture facilitates logic design  
— Multiple levels of switch matrices allow for performance-based routing  
— 100% routability and pin-out retention  
— Synchronous and asynchronous clocking, including dual-edge clocking  
— Asynchronous product- or sum-term set or reset  
— 16 to 64 output enables  
— Functions of up to 32 product terms  
Advanced capabilities for easy system integration  
— 3.3-V & 5-V JEDEC-compliant operations  
— IEEE 1149.1 compliant for boundary scan testing  
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port  
— PCI compliant (-5/-6/-7/-10/-12 speed grades)  
— Safe for mixed supply voltage system design  
— Bus-Friendly™ Inputs & I/Os  
— Individual output slew rate control  
— Hot socketing  
— Programmable security bit  
2
Advanced E CMOS process provides high performance, cost effective solutions  
Publication# 20446  
Amendment/0  
Rev: J  
Issue Date: April 2002  

M5-256/120-15YC/1 替代型号

型号 品牌 替代类型 描述 数据表
ISPLSI3256A-70LQ LATTICE

类似代替

In-System Programmable High Density PLD
ISPLSI3256A-70LQI LATTICE

类似代替

In-System Programmable High Density PLD

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