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M5-256/120-7AI

更新时间： 2024-10-29 05:23:19

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
47页	1091K
描述
Fifth Generation MACH Architecture

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中文翻译

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数据手册

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M5-256/120-7AI 数据手册

MACH 5 CPLD Family

Fifth Generation MACH Architecture

FEATURES

High logic densities and I/Os for increased logic integration

— 128 to 512 macrocell densities

— 68 to 256 I/Os

Wide selection of density and I/O combinations to support most application needs

— 6 macrocell density options

— 7 I/O options

— Up to 4 I/O options per macrocell density

— Up to 5 density & I/O options for each package

Performance features to ﬁt system needs

— 5.5 ns t Commercial, 7.5 ns t Industrial

— 182 MHz f

CNT

— Four programmable power/speed settings per block

Flexible architecture facilitates logic design

— Multiple levels of switch matrices allow for performance-based routing

— 100% routability and pin-out retention

— Synchronous and asynchronous clocking, including dual-edge clocking

— Asynchronous product- or sum-term set or reset

— 16 to 64 output enables

— Functions of up to 32 product terms

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— IEEE 1149.1 compliant for boundary scan testing

— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port

— PCI compliant (-5/-6/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system design

— Bus-Friendly™ Inputs & I/Os

— Individual output slew rate control

— Hot socketing

— Programmable security bit

Advanced E CMOS process provides high performance, cost effective solutions

Supported by ispDesignEXPERT™ softw are for rapid logic development

— Supports HDL design methodologies with results optimized for MACH 5 devices

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

Lattice and Third-party hardw are programming support

— LatticePRO™ software for in-system programmability support on PCs and Automated Test

Equipment

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,

and System General

Publication# 20446

Amendment/0

Rev: I

Issue Date: September 2000

12 3 4 5 6 7...47

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与M5-256/120-7AI相关器件

型号	品牌	获取价格	描述	数据表
M5-256/120-7HC	LATTICE	获取价格	Fifth Generation MACH Architecture
M5-256/120-7HI	LATTICE	获取价格	Fifth Generation MACH Architecture
M5-256/120-7VC	LATTICE	获取价格	Fifth Generation MACH Architecture
M5-256/120-7VI	LATTICE	获取价格	Fifth Generation MACH Architecture
M5-256/120-7YC	LATTICE	获取价格	Fifth Generation MACH Architecture
M5-256/120-7YC/1	LATTICE	获取价格	EE PLD, 7.5ns, 256-Cell, CMOS, PQFP160, PLASTIC, QFP-160
M5-256/120-7YI	LATTICE	获取价格	Fifth Generation MACH Architecture
M5-256/120-7YI/1	LATTICE	获取价格	EE PLD, 7.5ns, 256-Cell, CMOS, PQFP160, PLASTIC, QFP-160
M5-256/120-7YNC	LATTICE	获取价格	EE PLD, 7.5ns, CMOS, PQFP160, PLASTIC, QFP-160
M5-256/120-7YNC/1	LATTICE	获取价格	EE PLD, 7.5ns, CMOS, PQFP160, PLASTIC, QFP-160