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M5-256/120-12YNC PDF预览

M5-256/120-12YNC

更新时间: 2024-10-30 04:42:55
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
42页 938K
描述
EE PLD, 12ns, CMOS, PQFP160, PLASTIC, QFP-160

M5-256/120-12YNC 数据手册

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MACH 5 CPLD Family  
Fifth Generation MACH Architecture  
FEATURES  
High logic densities and I/Os for increased logic integration  
— 128 to 512 macrocell densities  
— 68 to 256 I/Os  
Wide selection of density and I/O combinations to support most application needs  
— 6 macrocell density options  
— 7 I/O options  
— Up to 4 I/O options per macrocell density  
— Up to 5 density & I/O options for each package  
Performance features to fit system needs  
— 5.5 ns t Commercial, 7.5 ns t Industrial  
PD  
PD  
— 182 MHz f  
CNT  
— Four programmable power/speed settings per block  
Flexible architecture facilitates logic design  
— Multiple levels of switch matrices allow for performance-based routing  
— 100% routability and pin-out retention  
— Synchronous and asynchronous clocking, including dual-edge clocking  
— Asynchronous product- or sum-term set or reset  
— 16 to 64 output enables  
— Functions of up to 32 product terms  
Advanced capabilities for easy system integration  
— 3.3-V & 5-V JEDEC-compliant operations  
— IEEE 1149.1 compliant for boundary scan testing  
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port  
— PCI compliant (-5/-6/-7/-10/-12 speed grades)  
— Safe for mixed supply voltage system design  
— Bus-Friendly™ Inputs & I/Os  
— Individual output slew rate control  
— Hot socketing  
— Programmable security bit  
2
Advanced E CMOS process provides high performance, cost effective solutions  
Publication# 20446  
Amendment/0  
Rev: J  
Issue Date: April 2002  

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