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M5-192/104-12HI

更新时间： 2024-02-06 16:19:14
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
47页 1092K
描述
Fifth Generation MACH Architecture

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M5-192/104-12HI 技术参数

是否Rohs认证：不符合生命周期：Transferred
Reach Compliance Code：unknown风险等级：5.72
Is Samacsys：N其他特性：YES
最大时钟频率：71 MHz系统内可编程：YES
JESD-30 代码：S-PQFP-G144JESD-609代码：e0
JTAG BST：YES专用输入次数：
I/O 线路数量：104宏单元数：192
端子数量：144最高工作温度：85 °C
最低工作温度：-40 °C组织：0 DEDICATED INPUTS, 104 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP144,1.2SQ
封装形状：SQUARE封装形式：FLATPACK
电源：5 V可编程逻辑类型：EE PLD
传播延迟：18 ns认证状态：Not Qualified
子类别：Programmable Logic Devices最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUADBase Number Matches：1

M5-192/104-12HI 数据手册

 浏览型号M5-192/104-12HI的Datasheet PDF文件第7页浏览型号M5-192/104-12HI的Datasheet PDF文件第8页浏览型号M5-192/104-12HI的Datasheet PDF文件第9页浏览型号M5-192/104-12HI的Datasheet PDF文件第11页浏览型号M5-192/104-12HI的Datasheet PDF文件第12页浏览型号M5-192/104-12HI的Datasheet PDF文件第13页 
MULTIPLE I/O AND DENSITY OPTIONS  
The MACH 5 family offers six macrocell densities in a number of I/O options. This allows designers  
to choose a device close to their logic density and I/O requirements, thus minimizing costs. For  
the same package type, every density has the same pin-out. With proper design considerations, a  
design can be moved to a higher or lower density part as required.  
IEEE 1149.1 - COMPLIANT BOUNDARY SCAN TESTABILITY  
Most MACH 5 devices have boundary scan registers and are compliant to the IEEE 1149.1 standard.  
This allows functional testing of the circuit board on which the device is mounted through a serial  
scan path that can access all critical logic nodes. Internal registers are linked internally, allowing  
test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and  
shifted out for verification. In addition, these devices can be linked into a board-level serial scan  
path for more complete board-level testing.  
IEEE 1149.1 - COMPLIANT IN-SYSTEM PROGRAMMING  
Programming devices in-system provides a number of significant benefits including: rapid  
prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications.  
All MACH 5 devices provide in-system programming (ISP) capability through their IEEE 1149.1-  
compliant Boundary Scan Test Access Port. By using the IEEE 1149.1-compliant Boundary Scan  
Test Access Port as the communication interface through which ISP is achieved, customers get the  
benefit of a standard, well-defined interface.  
MACH 5 devices can be programmed across the commercial temperature and voltage range. The  
PC-based LatticePRO software facilitates in-system programming of MACH 5 devices. LatticePRO  
software takes the JEDEC file output produced by design implementation software, along with  
information about the Boundary Scan chain, and creates a set of vectors that are used to drive the  
Boundary Scan chain. LatticePRO software can use these vectors to drive a Boundary Scan chain  
via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats  
understood by common automated test equipment. This equipment can then be used to program  
MACH 5 devices during the testing of a circuit board.  
PCI COMPLIANT  
MACH 5 devices in the -5/-6/-7/-10/-12 speed grades are compliant with the PCI Local Bus  
Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are  
fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to  
clamp the inputs as they rise above V because of their 5-V input tolerant feature. MACH 5  
CC  
devices provide the speed, drive, density, output enables and I/Os for the most complex PCI  
designs.  
10  
MACH 5 Family  
1...78910111213...47

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