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M5-192/104-12HI

更新时间： 2024-02-15 01:33:42

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
47页	1092K
描述
Fifth Generation MACH Architecture

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技术参数
数据手册

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M5-192/104-12HI 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
Reach Compliance Code：	unknown	风险等级：	5.72
Is Samacsys：	N	其他特性：	YES
最大时钟频率：	71 MHz	系统内可编程：	YES
JESD-30 代码：	S-PQFP-G144	JESD-609代码：	e0
JTAG BST：	YES	专用输入次数：
I/O 线路数量：	104	宏单元数：	192
端子数量：	144	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	0 DEDICATED INPUTS, 104 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP144,1.2SQ
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	18 ns	认证状态：	Not Qualified
子类别：	Programmable Logic Devices	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	QUAD	Base Number Matches：	1

M5-192/104-12HI 数据手册

MACH 5 TIMING MODEL

The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5

device, and at the same time, be easy to understand. This model accurately describes all

combinatorial and registered paths through the device, making a distinction between internal

feedback and external feedback. A signal uses internal feedback when it is fed back into the switch

matrix or block without having to go through the output buffer. The input register speciﬁcations

are also reported as internal feedback. When a signal is fed back into the switch matrix after having

gone through the output buffer, it is using external feedback.

The parameter, t , is deﬁned as the time it takes to go through the output buffer to the I/O pad.

BUF

If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is

followed by an “i”. By adding t

to this internal parameter, the external parameter is derived.

BUF

For example, t = t

+ t . A diagram representing the modularized MACH 5 timing model is

PDi

BUF

shown in Figure 7. Refer to the Technical Note entitled MACH 5 Timing and High Speed Design

for a more detailed discussion about the timing parameters.

(External Feedback)

(Internal Feedback)

COMB/DFF/

LATCH

t_SLW

OUT

t_{S (S/A)}

t_{H (S/A)}

t_SAL

t_HAL

t_SRR

t_PDi

t_{CO (S/A) i}

t_PDLi

t_GOAi

t_SRi

t_BUF

t_PL1

t_PL2

t_PL3

INPUT REG/

INPUT LATCH

t_BLK

t_SEG

t_CES

t_CEH

t_PT

t_{SIR (S/A)}

t_{HIR (S/A)}

t_SIL

t_{CO (S/A) i}

t_EA

t_ER

t_PDILi

t_GOAi

t_SRi

t_HIL

t_SRR

t_CES

t_CEH

PIN CLK

20446G-014

Figure 7. MACH 5 Timing Model

MACH 5 Family

1...6 7 8910 11 12...47

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