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M48Z128Y-85CS1 PDF预览

M48Z128Y-85CS1

更新时间: 2024-11-04 22:10:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
17页 108K
描述
1 Mbit 128Kb x8 ZEROPOWER SRAM

M48Z128Y-85CS1 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSOP包装说明:TSOP-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.89Is Samacsys:N
最长访问时间:85 ns其他特性:REQUIRES A SNAPHAT BATTERY PACKAGE
JESD-30 代码:R-PDSO-G32JESD-609代码:e0
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:TSSOP32,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
最大待机电流:0.004 A子类别:SRAMs
最大压摆率:0.105 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

M48Z128Y-85CS1 数据手册

 浏览型号M48Z128Y-85CS1的Datasheet PDF文件第2页浏览型号M48Z128Y-85CS1的Datasheet PDF文件第3页浏览型号M48Z128Y-85CS1的Datasheet PDF文件第4页浏览型号M48Z128Y-85CS1的Datasheet PDF文件第5页浏览型号M48Z128Y-85CS1的Datasheet PDF文件第6页浏览型号M48Z128Y-85CS1的Datasheet PDF文件第7页 
M48Z128  
M48Z128Y  
1 Mbit (128Kb x8) ZEROPOWER SRAM  
INTEGRATED LOW POWER SRAM,  
POWER-FAIL CONTROL CIRCUIT and  
BATTERY  
CONVENTIONAL SRAM OPERATION;  
UNLIMITED WRITE CYCLES  
32  
10 YEARS of DATA RETENTION in the  
1
ABSENCE of POWER  
PMDIP32 (PM)  
Module  
AUTOMATIC POWER-FAIL CHIP DESELECT  
and WRITE PROTECTION  
SNAPHAT (SH)  
Battery  
WRITE PROTECT VOLTAGES  
(V  
= Power-fail Deselect Voltage):  
PFD  
– M48Z128: 4.50V V  
4.75V  
PFD  
– M48Z128Y: 4.20V V  
4.50V  
PFD  
BATTERY INTERNALLY ISOLATED UNTIL  
POWER IS APPLIED  
PIN and FUNCTION COMPATIBLE with  
JEDEC STANDARD 128K x 8 SRAMs  
TSOP32  
(8 x 20mm)  
SURFACE MOUNT CHIP SET PACKAGING  
INCLUDES a 28-PIN SOIC and a 32-LEAD  
TSOP (SNAPHAT TOP TO BE ORDERED  
SEPARATELY)  
SOH28  
Surface Mount Chip Set Solution (CS)  
SOIC PACKAGE PROVIDES DIRECT  
CONNECTION for a SNAPHAT TOP WHICH  
CONTAINS the BATTERY  
Figure 1. Logic Diagram  
V
SNAPHAT HOUSING (BATTERY) IS  
CC  
REPLACEABLE  
17  
8
Table 1. Signal Names  
A0-A16  
W
DQ0-DQ7  
A0-A16  
Address Inputs  
Data Inputs / Outputs  
Chip Enable  
DQ0-DQ7  
M48Z128  
M48Z128Y  
E
E
G
W
Output Enable  
Write Enable  
G
V
Supply Voltage  
Ground  
CC  
V
V
SS  
SS  
AI01194  
NC  
Not Connected Internally  
June 2000  
1/17  

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