M48Z128Y-120PM1

更新时间： 2024-11-04 22:11:23

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		静态存储器
页数	文件大小	规格书
17页	108K
描述
1 Mbit 128Kb x8 ZEROPOWER SRAM

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中文翻译

获取价格

数据手册

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M48Z128Y-120PM1 数据手册

M48Z128

M48Z128Y

1 Mbit (128Kb x8) ZEROPOWER SRAM

■ INTEGRATED LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and

BATTERY

■ CONVENTIONAL SRAM OPERATION;

UNLIMITED WRITE CYCLES

■ 10 YEARS of DATA RETENTION in the

ABSENCE of POWER

PMDIP32 (PM)

Module

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

SNAPHAT (SH)

Battery

■ WRITE PROTECT VOLTAGES

= Power-fail Deselect Voltage):

PFD

– M48Z128: 4.50V ≤ V

≤ 4.75V

PFD

– M48Z128Y: 4.20V ≤ V

≤ 4.50V

PFD

■ BATTERY INTERNALLY ISOLATED UNTIL

POWER IS APPLIED

■ PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 128K x 8 SRAMs

TSOP32

(8 x 20mm)

■ SURFACE MOUNT CHIP SET PACKAGING

INCLUDES a 28-PIN SOIC and a 32-LEAD

TSOP (SNAPHAT TOP TO BE ORDERED

SEPARATELY)

SOH28

Surface Mount Chip Set Solution (CS)

■ SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP WHICH

CONTAINS the BATTERY

Figure 1. Logic Diagram

■ SNAPHAT HOUSING (BATTERY) IS

REPLACEABLE

Table 1. Signal Names

A0-A16

DQ0-DQ7

A0-A16

Address Inputs

Data Inputs / Outputs

Chip Enable

DQ0-DQ7

M48Z128

M48Z128Y

Output Enable

Write Enable

Supply Voltage

Ground

AI01194

Not Connected Internally

June 2000

1/17

12 3 4 5 6 7...17

中文翻译

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