Datasheet > M48Z08-100MH6TR

M48Z08-100MH6TR

更新时间： 2024-11-10 22:15:35

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		静态存储器
页数	文件大小	规格书
18页	143K
描述
64 Kbit 8Kb x 8 ZEROPOWER SRAM

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中文翻译

获取价格

数据手册

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M48Z08-100MH6TR 数据手册

M48Z08

M48Z18

64 Kbit (8Kb x 8) ZEROPOWER SRAM

INTEGRATED ULTRA LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and

BATTERY

SNAPHAT (SH)

Battery

UNLIMITED WRITE CYCLES

READ CYCLE TIME EQUALS WRITE CYCLE

TIME

AUTOMATIC POWER-FAIL CHIP DESELECT and

WRITE PROTECTION

WRITE PROTECT VOLTAGES

(V_PFD= Power-fail Deselect Voltage):

– M48Z08: 4.50V ≤ V_PFD≤ 4.75V

– M48Z18: 4.20V ≤ V_PFD≤ 4.50V

SELF-CONTAINED BATTERY in the CAPHAT

DIP PACKAGE

PCDIP28 (PC)

Battery CAPHAT

SOH28 (MH)

PACKAGING INCLUDES a 28 LEAD SOIC

and SNAPHAT^®TOP (to be Ordered

Separately)

SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP which

CONTAINS the BATTERY

PIN and FUNCTION COMPATIBLE with the

DS1225 and JEDEC STANDARD 8K x 8

SRAMs

Figure 1. Logic Diagram

DESCRIPTION

The M48Z08/18 ZEROPOWER^®RAM is an 8K x

8 non-volatile static RAM which is pin and func-

tional compatible with the DS1225. The monolithic

chip is available in two special packages to provide

a highly integrated battery backed-up memory so-

lution.

A0-A12

DQ0-DQ7

M48Z08

M48Z18

Table 1. Signal Names

A0-A12

Address Inputs

Data Inputs / Outputs

Chip Enable

DQ0-DQ7

Output Enable

Write Enable

Supply Voltage

Ground

AI01022

V_CC

V_SS

March 1999

1/18

12 3 4 5 6 7...18

中文翻译

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