Datasheet > M48Z08-150PC6

M48Z08-150PC6

更新时间： 2024-11-10 22:51:39

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		静态存储器
页数	文件大小	规格书
12页	88K
描述
16 Kbit 2Kb x 8 ZEROPOWER SRAM

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中文翻译

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数据手册

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M48Z08-150PC6 数据手册

M48Z02

M48Z12

16 Kbit (2Kb x 8) ZEROPOWER SRAM

INTEGRATED ULTRA LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and

BATTERY

UNLIMITED WRITE CYCLES

READ CYCLE TIME EQUALS WRITE CYCLE

TIME

AUTOMATIC POWER-FAIL CHIP DESELECT and

WRITE PROTECTION

WRITE PROTECT VOLTAGES

(V_PFD= Power-fail Deselect Voltage):

– M48Z02: 4.50V ≤ V_PFD≤ 4.75V

– M48Z12: 4.20V ≤ V_PFD≤ 4.50V

PCDIP24 (PC)

Battery CAPHAT

SELF-CONTAINED BATTERY in the CAPHAT

DIP PACKAGE

PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 2K x 8 SRAMs

Figure 1. Logic Diagram

DESCRIPTION

The M48Z02/12 ZEROPOWER^®RAM is a 2K x 8

non-volatile static RAM which is pin and functional

compatible with the DS1220.

A special 24 pin 600mil DIP CAPHAT package

houses the M48Z02/12 silicon with a long life lith-

ium button cell to form a highly integrated battery

backed-up memory solution.

The M48Z02/12 button cell has sufficient capacity

and storage life to maintain data and clockfunction-

ality for an accumulated time period of at least 10

years in the absence of power over the operating

temperature range.

A0-A10

DQ0-DQ7

M48Z02

M48Z12

Table 1. Signal Names

A0-A10

Address Inputs

Data Inputs / Outputs

Chip Enable

DQ0-DQ7

Output Enable

Write Enable

Supply Voltage

Ground

AI01186

V_CC

V_SS

May 1999

1/12

12 3 4 5 6 7...12

中文翻译

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