Datasheet > M471B6474DZ1-CF7

M471B6474DZ1-CF7

更新时间： 2024-02-24 18:32:57

品牌	Logo	应用领域
三星 - SAMSUNG		时钟动态存储器双倍数据速率内存集成电路
页数	文件大小	规格书
45页	805K
描述
DDR DRAM Module, 64MX64, 0.4ns, CMOS, ROHS COMPLIANT, SO-DIMM-204

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M471B6474DZ1-CF7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	DMA
包装说明：	DIMM, DIMM204,24	针数：	204
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.36	风险等级：	5.84
访问模式：	SINGLE BANK PAGE BURST	最长访问时间：	0.4 ns
其他特性：	AUTO/SELF REFRESH	最大时钟频率 (fCLK)：	400 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-XDMA-N204
内存密度：	4294967296 bit	内存集成电路类型：	DDR DRAM MODULE
内存宽度：	64	湿度敏感等级：	3
功能数量：	1	端口数量：	1
端子数量：	204	字数：	67108864 words
字数代码：	64000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：
组织：	64MX64	输出特性：	3-STATE
封装主体材料：	UNSPECIFIED	封装代码：	DIMM
封装等效代码：	DIMM204,24	封装形状：	RECTANGULAR
封装形式：	MICROELECTRONIC ASSEMBLY	峰值回流温度（摄氏度）：	260
电源：	1.5 V	认证状态：	Not Qualified
刷新周期：	8192	自我刷新：	YES
最大待机电流：	0.04 A	子类别：	DRAMs
最大压摆率：	1.12 mA	最大供电电压 (Vsup)：	1.575 V
最小供电电压 (Vsup)：	1.425 V	标称供电电压 (Vsup)：	1.5 V
表面贴装：	NO	技术：	CMOS
温度等级：	OTHER	端子形式：	NO LEAD
端子节距：	0.6 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

M471B6474DZ1-CF7 数据手册

浏览型号M471B6474DZ1-CF7的Datasheet PDF文件第10页

Unbuffered SoDIMM

DDR3 SDRAM

6.0 Input/Output Functional Description

Symbol

Type

Function

The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and

falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera-

tions is synchronized to the input clock.

CK0-CK1

Input

Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks,

CKE low initiates the Power Down mode or the Self Refresh mode.

CKE0-CKE1

S0-S1

Input

Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high.

When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is

selected by S0; Rank 1 is selected by S1.

When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define

the operation to be executed by the SDRAM.

RAS, CAS, WE

BA0-BA2

Input

Selects which DDR3 SDRAM internal bank of eight is activated.

ODT0-ODT1

Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register.

During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of

CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the

cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke

autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-

BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle,

AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-

charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre-

charge.A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-thefly) will be

performed (HIGH, no burst chop; LOW, burst chopped)

A0-A9,

A10/AP,

A11

A12/BC

A13-A15

Input

DQ0-DQ63

DM0-DM7

I/O

Data Input/Output pins.

The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input

data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.

Input

The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is

sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3

SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to

the crosspoint of respective DQS and DQS.

DQS0-DQS7

I/O

V_DD,V_DDSPD,

V_SS

Supply

I/O

Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.

Reference voltage for SSTL15 inputs.

V_REFDQ,

V_REFCA

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be

connected from the SDA bus line to V_DDSPDon the system planar to act as a pull up.

SDA

SCL

SA0-SA1

TEST

Input

I/O

This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.

Address pins used to select the Serial Presence Detect and Temp sensor base address.

The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules

RESET In Active Low This signal resets the DDR3 SDRAM

RESET

Input

7 of 45

Rev. 1.2 August 2008

1...4 5 678 9 10...45

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与M471B6474DZ1-CF7相关器件

型号	品牌	获取价格	描述	数据表
M471B6474DZ1-CG8	SAMSUNG	获取价格	DDR DRAM Module, 64MX64, CMOS, ROHS COMPLIANT, SO-DIMM-204
M471B6474DZ1-CH9	SAMSUNG	获取价格	DDR DRAM Module, 64MX64, 0.255ns, CMOS, ROHS COMPLIANT, SO-DIMM-204
M471CI8AE	NUVOTON	获取价格	WLCSP100
M471KI8AE	NUVOTON	获取价格	LQFP128
M471MD6AE	NUVOTON	获取价格	LQFP44
M471R1E6AE	NUVOTON	获取价格	LQFP64
M471SE6AE	NUVOTON	获取价格	LQFP64
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