Datasheet > M471B5673GB0-CF8

M471B5673GB0-CF8

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器双倍数据速率
页数	文件大小	规格书
37页	1085K
描述
DDR DRAM, 256MX64, 0.6ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, SODIMM-204

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M471B5673GB0-CF8 数据手册

Rev. 1.1

Unbuffered SODIMM

datasheet

DDR3 SDRAM

5. Pin Description

Pin Name

Description

Number

Pin Name

Description

Data Input/Output

Number

CK0, CK1

Clock Inputs, positive line

DQ0-DQ63

Data Masks/ Data strobes,

Termination data strobes

Clock Inputs, negative line

DM0-DM7

CKE0, CKE1 Clock Enables

DQS0-DQS7 Data strobes

RAS

CAS

Row Address Strobe

DQS0-DQS7 Data strobes complement

Column Address Strobe

Write Enable

RESET

TEST

V_DD

Reset Pin

Logic Analyzer specific test pin (No connect

on SODIMM)

S0, S1

Chip Selects

Core and I/O Power

Ground

A0-A9, A11,

A13-A15

V_SS

Address Inputs

V_REFDQ

V_REFCA

A10/AP

Address Input/Autoprecharge

Input/Output Reference

V_DDSPD

V_TT

A12/BC

Address Input/Burst chop

SDRAM Bank Addresses

SPD and Temp sensor Power

BA0-BA2

Termination Voltage

Reserved for future use

Total

ODT0, ODT1 On-die termination control

SCL

SDA

Serial Presence Detect (SPD) Clock Input

204

SPD Data Input/Output

SPD Address

SA0-SA1

NOTE:

*The V and V

pins are tied common to a single power-plane on these designs.

DDQ

- 6 -

1...3 4 567 8 9...37

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