Rev. 1.1
Unbuffered SODIMM
datasheet
DDR3 SDRAM
Table Of Contents
204pin Unbuffered SODIMM based on 1Gb G-die
1. DDR3 Unbuffered SODIMM Ordering Information........................................................................................................4
2. Key Features.................................................................................................................................................................4
3. Address Configuration ..................................................................................................................................................4
4. x64 DIMM Pin Configurations (Front side/Back Side)...................................................................................................5
5. Pin Description .............................................................................................................................................................6
6. Input/Output Functional Description..............................................................................................................................7
7. Function Block Diagram:...............................................................................................................................................8
7.1 1GB, 128Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs)..................................................................... 8
7.2 2GB, 256Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................... 9
8. Absolute Maximum Ratings ..........................................................................................................................................10
8.1 Absolute Maximum DC Ratings............................................................................................................................... 10
8.2 DRAM Component Operating Temperature Range ................................................................................................ 10
9. AC & DC Operating Conditions.....................................................................................................................................10
9.1 Recommended DC Operating Conditions (SSTL-15).............................................................................................. 10
10. AC & DC Input Measurement Levels..........................................................................................................................11
10.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 11
10.2 VREF Tolerances.................................................................................................................................................... 12
10.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 13
10.3.1. Differential Signals Definition ......................................................................................................................... 13
10.3.2. Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS) ................................................ 13
10.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 14
10.3.4. Differential Input Cross Point Voltage ............................................................................................................ 15
10.4 Slew Rate Definition for Single Ended Input Signals............................................................................................. 15
10.5 Slew rate definition for Differential Input Signals................................................................................................... 15
11. AC & DC Output Measurement Levels .......................................................................................................................16
11.1 Single Ended AC and DC Output Levels............................................................................................................... 16
11.2 Differential AC and DC Output Levels................................................................................................................... 16
11.3 Single-ended Output Slew Rate ............................................................................................................................ 16
11.4 Differential Output Slew Rate ................................................................................................................................ 17
12. DIMM IDD specification definition...............................................................................................................................18
13. IDD SPEC Table.........................................................................................................................................................20
14. Input/Output Capacitance ...........................................................................................................................................21
15. iElectrical Characteristics and AC timing ....................................................................................................................22
15.1 Refresh Parameters by Device Density................................................................................................................. 22
15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 22
15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin................................................................. 22
15.3.1. Speed Bin Table Notes .................................................................................................................................. 27
16. Timing Parameters by Speed Grade ..........................................................................................................................28
16.1 Jitter Notes ............................................................................................................................................................ 34
16.2 Timing Parameter Notes........................................................................................................................................ 35
17. Physical Dimensions :.................................................................................................................................................36
17.1 128Mbx8 based 128Mx64 Module (1 Rank) - M471B2873GB0............................................................................ 36
17.2 128Mbx8 based 256Mx64 Module (2 Ranks) - M471B5673GB0.......................................................................... 37
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