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M390S6450CT1-C7A PDF预览

M390S6450CT1-C7A

更新时间: 2024-01-02 17:00:53
品牌 Logo 应用领域
三星 - SAMSUNG 光电二极管动态存储器
页数 文件大小 规格书
12页 222K
描述
64Mx72 SDRAM DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD

M390S6450CT1-C7A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM168
针数:168Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.92Is Samacsys:N
访问模式:SINGLE BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N168
内存密度:4831838208 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:72湿度敏感等级:1
功能数量:1端口数量:1
端子数量:168字数:67108864 words
字数代码:64000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM168封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):225
电源:3.3 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
最大待机电流:0.038 A子类别:DRAMs
最大压摆率:2.75 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

M390S6450CT1-C7A 数据手册

 浏览型号M390S6450CT1-C7A的Datasheet PDF文件第1页浏览型号M390S6450CT1-C7A的Datasheet PDF文件第2页浏览型号M390S6450CT1-C7A的Datasheet PDF文件第3页浏览型号M390S6450CT1-C7A的Datasheet PDF文件第5页浏览型号M390S6450CT1-C7A的Datasheet PDF文件第6页浏览型号M390S6450CT1-C7A的Datasheet PDF文件第7页 
M390S6450CT1  
PC133 Registered DIMM  
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)  
*2  
REG  
*1  
DOUT  
Control Signal(RAS,CAS,WE)  
*3  
*1. Register Input  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLK  
RAS  
CAS  
WE  
*2. Register Output  
RAS  
td  
tr  
td  
tr  
CAS  
WE  
*3. SDRAM  
CAS latency(refer to *1)  
=2CLK+1CLK  
1CLK  
tSAC  
tRAC(refer to *1)  
tRAC(refer to *2)  
Qa0 Qa1 Qa2 Qa3  
Db0 Db1 Db2 Db3  
DQ  
CAS latency(refer to *2)  
=2CLK  
tRDL  
Row Active  
Precharge  
Command  
Write  
Command  
Row Active  
Read  
Command  
Precharge  
Command  
td, tr = Delay of register (74ALVCF162835)  
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal  
because of the buffering in register (74ALVCF162835). Therefore, Input/Output signals of read/write function should be  
issued 1CLK earlier as compared to Unbuffered DIMMs.  
2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.  
: Don¢t care  
Rev. 0.2 Sept. 2001  

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