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M374S6453CTS-L7C PDF预览

M374S6453CTS-L7C

更新时间: 2024-11-11 21:55:07
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器PC
页数 文件大小 规格书
11页 167K
描述
M374S6453CTS PC133/PC100 Unbuffered SDRAM DIMM

M374S6453CTS-L7C 数据手册

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PC133/PC100 Unbuffered DIMM  
M374S6453CTS  
M374S6453CTS SDRAM DIMM  
64Mx72 SDRAM DIMM with ECC based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD  
GENERAL DESCRIPTION  
FEATURE  
• Performance range  
The Samsung M374S6453CTS is a 64M bit x 72 Synchronous  
Dynamic RAM high density memory module. The Samsung  
M374S6453CTS consists of eighteen CMOS 32M x 8 bit with  
4banks Synchronous DRAMs in TSOP-II 400mil package and a  
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy  
substrate. Two 0.1uF decoupling capacitors are mounted on the  
printed circuit board in parallel for each SDRAM.  
Part No.  
Max Freq. (Speed)  
133MHz@CL=2  
133MHz@CL=3  
100MHz@ CL=2  
100MHz@ CL=3  
M374S6453CTS-L7C/C7C  
M374S6453CTS-L7A/C7A  
M347S6453CTS-L1H/C1H  
M347S6453CTS-L1L/C1L  
• Burst mode operation  
The M374S6453CTS is a Dual In-line Memory Module and is  
intended for mounting into 168-pin edge connector sockets.  
Synchronous design allows precise cycle control with the use of  
system clock. I/O transactions are possible on every clock cycle.  
Range of operating frequencies, programmable latencies allows  
the same device to be useful for a variety of high bandwidth, high  
performance memory system applications.  
• Auto & self refresh capability (8192 Cycles/64ms)  
• LVTTL compatible inputs and outputs  
• Single 3.3V ± 0.3V power supply  
• MRS cycle with address key programs  
Latency (Access from column address)  
Burst length (1, 2, 4, 8 & Full page)  
Data scramble (Sequential & Interleave)  
• All inputs are sampled at the positive going edge of the  
system clock  
• Serial presence detect with EEPROM  
• PCB : Height (1,375mil), double sided component  
PIN CONFIGURATIONS (Front side/back side)  
PIN NAMES  
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back  
Pin Name  
A0 ~ A12  
Function  
Address input (Multiplexed)  
Select bank  
1
2
3
4
5
6
7
8
9
VSS  
29 DQM1 57 DQ18 85  
VSS 113 DQM5 141 DQ50  
BA0 ~ BA1  
DQ0 ~ DQ63  
CB0 ~ 7  
58  
59  
60  
61  
62  
DQ0 30  
DQ1 31  
DQ2 32  
DQ3 33  
CS0  
DU  
VSS  
A0  
DQ19 86 DQ32 114 CS1 142 DQ51  
Data input/output  
VDD  
87 DQ33 115 RAS 143 VDD  
DQ20 88 DQ34 116 VSS 144 DQ52  
Check bit (Data-in/data-out)  
NC  
*VREF 90  
89 DQ35 117  
VDD 118  
A1  
A3  
A5  
A7  
A9  
145 NC  
146 *VREF  
147 NC  
148 VSS  
149 DQ53  
CLK0 ~ CLK3 Clock input  
VDD  
34  
A2  
CKE0 ~ CKE1 Clock enable input  
DQ4 35  
DQ5 36  
DQ6 37  
A4  
A6  
A8  
63 CKE1 91 DQ36 119  
64  
65 DQ21 93 DQ38 121  
66  
VSS  
92 DQ37 120  
CS0 ~ CS3  
RAS  
Chip select input  
Row address strobe  
Column address strobe  
Write enable  
10 DQ7 38 A10/AP  
DQ22 94 DQ39 122 BA0 150 DQ54  
67 DQ23 95 DQ40 123 A11 151 DQ55  
68  
69 DQ24 97 DQ41 125 CLK1 153 DQ56  
70  
71 DQ26 99 DQ43 127 VSS 155 DQ58  
CAS  
11 DQ8 39  
12 40  
13 DQ9 41  
BA1  
VDD  
VDD  
WE  
VSS  
VSS  
96  
VSS 124 VDD 152 VSS  
DQM0 ~ 7  
VDD  
DQM  
14 DQ10 42 CLK0  
DQ25 98 DQ42 126 A12 154 DQ57  
Power supply (3.3V)  
Ground  
15 DQ11 43  
16 DQ12 44  
17 DQ13 45  
VSS  
DU  
CS2  
VSS  
72  
73  
74  
DQ27 100 DQ44 128 CKE0 156 DQ59  
VDD 101 DQ45 129 CS3 157 VDD  
DQ28 102 VDD 130 DQM6 158 DQ60  
*VREF  
SDA  
Power supply for reference  
Serial data I/O  
Serial clock  
18  
VDD  
46 DQM2  
19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61  
SCL  
76  
77 DQ31 105 CB4 133 VDD 161 DQ63  
78  
79 CLK2 107 VSS 135 NC 163 CLK3  
80  
81 *WP 109 NC 137 CB7 165 **SA0  
82  
20 DQ15 48  
DU  
VDD  
NC  
DQ30 104 DQ47 132 *A13 160 DQ62  
SA0 ~ 2  
*WP  
Address in EEPROM  
Write protection  
Don¢t use  
21 CB0  
22 CB1  
49  
50  
51  
52  
53  
54  
VSS 106 CB5 134 NC 162 VSS  
23  
24  
25  
26  
27  
VSS  
NC  
NC  
VDD  
WE  
NC  
DU  
CB2  
CB3  
VSS  
NC 108 NC 136 CB6 164 NC  
NC  
No connection  
**SDA 110 VDD 138 VSS 166 **SA1  
*
These pins are not used in this module.  
** These pins should be NC in the system  
55 DQ16 83 **SCL 111 CAS 139 DQ48 167 **SA2  
84  
28 DQM0 56 DQ17  
VDD 112 DQM4 140 DQ49 168 VDD  
which does not support SPD.  
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.  
REV. 0.1 Sept. 2001  

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