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M366S0924BTS-C1L PDF预览

M366S0924BTS-C1L

更新时间: 2024-11-06 15:39:43
品牌 Logo 应用领域
三星 - SAMSUNG 时钟动态存储器内存集成电路
页数 文件大小 规格书
9页 127K
描述
Synchronous DRAM Module, 8MX64, 6ns, CMOS, DIMM-168

M366S0924BTS-C1L 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM168
针数:168Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.28
风险等级:5.92访问模式:FOUR BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N168内存密度:536870912 bit
内存集成电路类型:SYNCHRONOUS DRAM MODULE内存宽度:64
湿度敏感等级:1功能数量:1
端口数量:1端子数量:168
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM168
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified刷新周期:4096
自我刷新:YES最大待机电流:0.004 A
子类别:DRAMs最大压摆率:0.84 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

M366S0924BTS-C1L 数据手册

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M366S0924BTS  
PC100 Unbuffered DIMM  
M366S0924BTS SDRAM DIMM  
8Mx64 SDRAM DIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD  
GENERAL DESCRIPTION  
FEATURE  
The Samsung M366S0924BTS is a 8M bit x 64 Synchronous  
Dynamic RAM high density memory module. The Samsung  
M366S0924BTS consists of four CMOS 8M x 16 bit with 4banks  
Synchronous DRAMs in TSOP-II 400mil package and a 2K  
EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy  
substrate. Two 0.1uF decoupling capacitors are mounted on the  
printed circuit board in parallel for each SDRAM.  
• Performance range  
Part No.  
Max Freq. (Speed)  
125MHz (8ns @ CL=3)  
100MHz (10ns @ CL=2)  
100MHz (10ns @ CL=3)  
M366S0924BTS-C80  
M366S0924BTS-C1H  
M366S0924BTS-C1L  
Burst mode operation  
• Auto & self refresh capability (4096 Cycles/64ms)  
• LVTTL compatible inputs and outputs  
• Single 3.3V ± 0.3V power supply  
The M366S0924BTS is a Dual In-line Memory Module and is  
intended for mounting into 168-pin edge connector sockets.  
Synchronous design allows precise cycle control with the use of  
system clock. I/O transactions are possible on every clock cycle.  
Range of operating frequencies, programmable latencies allows  
the same device to be useful for a variety of high bandwidth,  
high performance memory system applications.  
• MRS cycle with address key programs  
Latency (Access from column address)  
Burst length (1, 2, 4, 8 & Full page)  
Data scramble (Sequential & Interleave)  
• All inputs are sampled at the positive going edge of the  
system clock  
• Serial presence detect with EEPROM  
• PCB : Height (1,000mil) , single sided component  
PIN CONFIGURATIONS (Front side/back side)  
PIN NAMES  
Pin  
Pin Front Pin Front  
Front Pin Back Pin Back Pin Back  
Pin Name  
A0 ~ A11  
Function  
Address input (Multiplexed)  
Select bank  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
1
2
3
4
5
6
7
8
9
VSS  
29 DQM1  
DQ18 85  
DQ19 86 DQ32 114 *CS1 142 DQ51  
87 DQ33 115 RAS 143 VDD  
DQ20 88 DQ34 116 VSS 144 DQ52  
VSS 113 DQM5 141 DQ50  
BA0 ~ BA1  
DQ0 30  
DQ1 31  
DQ2 32  
DQ3 33  
CS0  
DU  
VSS  
A0  
DQ0 ~ DQ63 Data input/output  
VDD  
CLK0, CLK2  
CKE0  
CS0, CS2  
RAS  
Clock input  
NC  
*VREF 90  
*CKE1 91 DQ36 119  
92 DQ37 120  
DQ21 93 DQ38 121  
89 DQ35 117  
A1  
A3  
A5  
A7  
A9  
145 NC  
146 *VREF  
147 NC  
148 VSS  
149 DQ53  
Clock enable input  
Chip select input  
Row address strobe  
Column address strobe  
Write enable  
VDD  
34  
A2  
VDD 118  
DQ4 35  
DQ5 36  
DQ6 37  
A4  
A6  
A8  
VSS  
CAS  
10 DQ7 38 A10/AP  
DQ22 94 DQ39 122 BA0 150 DQ54  
DQ23 95 DQ40 123 A11 151 DQ55  
WE  
11 DQ8 39  
12 40  
13 DQ9 41  
BA1  
VDD  
VDD  
DQM0 ~ 7  
VDD  
DQM  
VSS  
VSS  
96  
VSS 124 VDD 152 VSS  
DQ24 97 DQ41 125 *CLK1 153 DQ56  
DQ25 98 DQ42 126 *A12 154 DQ57  
DQ26 99 DQ43 127 VSS 155 DQ58  
Power supply (3.3V)  
Ground  
14 DQ10 42 CLK0  
VSS  
15 DQ11 43  
16 DQ12 44  
17 DQ13 45  
VSS  
NC  
CS2  
*VREF  
SDA  
Power supply for reference  
Serial data I/O  
Serial clock  
72 DQ27 100 DQ44 128 CKE0 156 DQ59  
73  
74  
75  
76  
VDD 101 DQ45 129 *CS3 157 VDD  
DQ28 102 VDD 130 DQM6 158 DQ60  
DQ29 103 DQ46 131 DQM7 159 DQ61  
DQ30 104 DQ47 132 *A13 160 DQ62  
18  
VDD  
46 DQM2  
SCL  
19 DQ14 47 DQM3  
SA0 ~ 2  
WP  
Address in EEPROM  
Write protection  
Don¢t use  
20 DQ15 48  
21 *CB0 49  
22 *CB1 50  
NC  
VDD  
NC  
NC  
77 DQ31 105 *CB4 133 VDD 161 DQ63  
78  
79  
80  
81  
82  
83  
84  
VSS 106 *CB5 134 NC 162 VSS  
CLK2 107 VSS 135 NC 163 *CLK3  
NC 108 NC 136 *CB6 164 NC  
WP 109 NC 137 *CB7 165 **SA0  
**SDA 110 VDD 138 VSS 166 **SA1  
**SCL 111 CAS 139 DQ48 167 **SA2  
VDD 112 DQM4 140 DQ49 168 VDD  
DU  
23  
24  
25  
26  
27  
VSS  
NC  
NC  
VDD  
WE  
51  
NC  
No connection  
52 *CB2  
53 *CB3  
54  
*
These pins are not used in this module.  
** These pins should be NC in the system  
VSS  
55 DQ16  
which does not support SPD.  
28 DQM0 56 DQ17  
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.  
Rev. 0.0 Aug. 1999  

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