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M29F002NT-120XK6TR PDF预览

M29F002NT-120XK6TR

更新时间： 2024-01-23 12:53:56
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存内存集成电路
页数 文件大小 规格书
29页 199K
描述
2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory

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M29F002NT-120XK6TR 技术参数

生命周期：Transferred零件包装代码：QFJ
包装说明：QCCJ,针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.36
最长访问时间：120 ns其他特性：20 YEARS DATA RETENTION; 100000 PROGRAM/ERASE CYCLES
启动块：TOP数据保留时间-最小值：20
JESD-30 代码：R-PQCC-J32长度：13.995 mm
内存密度：2097152 bit内存集成电路类型：FLASH
内存宽度：8功能数量：1
端子数量：32字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX8封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：RECTANGULAR
封装形式：CHIP CARRIER并行/串行：PARALLEL
编程电压：5 V认证状态：Not Qualified
座面最大高度：3.56 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
类型：NOR TYPE宽度：11.455 mm

M29F002NT-120XK6TR 数据手册

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M29F002T, M29F002NT, M29F002B  
Table 8. Instructions (1)  
Mne.  
Instr.  
Cyc.  
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.  
Addr. (3,7)  
Data  
X
1+  
Read Memory Array until a new write cycle is initiated.  
Read/Reset  
RD (2,4)  
F0h  
Memory Array  
Addr. (3,7)  
555h  
AAh  
AAAh  
55h  
555h  
F0h  
Read Memory Array until a new write  
cycle is initiated.  
3+  
3+  
Data  
Addr. (3,7)  
555h  
AAAh  
555h  
Read Electronic Signature or Block  
Protection Status until a new write cycle  
is initiated. See Note 5 and 6.  
AS (4) Auto Select  
Data  
AAh  
55h  
90h  
Program  
Address  
Addr. (3,7)  
555h  
AAAh  
555h  
Read Data Polling or Toggle  
Bit until Program completes.  
PG  
BE  
Program  
4
6
Program  
Data  
Data  
AAh  
55h  
A0h  
Block  
Additional  
Addr. (3,7)  
555h  
AAAh  
555h  
555h  
AAAh  
Address Block (8)  
Block Erase  
Chip Erase  
Data  
AAh  
555h  
AAh  
X
55h  
AAAh  
55h  
80h  
555h  
80h  
AAh  
555h  
AAh  
55h  
AAAh  
55h  
30h  
555h  
10h  
30h  
Addr. (3,7)  
CE  
ES (10)  
ER  
6
1
1
Note 9  
Data  
Addr. (3,7)  
Data  
Erase  
Suspend  
Read until Toggle stops, then read all the data needed from  
any Block(s) not being erased then Resume Erase.  
B0h  
X
Addr. (3,7)  
Erase  
Resume  
Read Data Polling or Toggle Bits until Erase completes or  
Erase is suspended another time  
Data  
30h  
Notes: 1. Commands not interpreted in this table will default to read array mode.  
2. Await of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode  
before starting any new operation (see Table 14 and Figure 9).  
3. X = Don’t Care.  
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after  
the command cycles.  
5. Signature Address bits A0,A1 at VIL willoutput Manufacturer code (20h). Address bits A0 at VIH and A1 at VIL will output  
Device code.  
6. Block Protection Address: A0 at VIL, A1 at VIH and A13-A17 within the Block will output the Block Protection status.  
7. For Coded cycles address inputs A12-A17are don’t care.  
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry,  
timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description).  
When full command is entered, read Data Polling or Togglebit until Erase is completed or suspended.  
9. Read Data Polling, Toggle bits or RB until Erase completes.  
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.  
Theinstructions require from 1 to 6 cycles, the first  
or first three of which are always write operations  
usedtoinitiatethe instruction.Theyare followedby  
either further write cycles to confirm the first com-  
mand or executethe commandimmediately.Com-  
mand sequencing must be followed exactly. Any  
invalid combination of commands will reset the  
device to Read Array. The increased number of  
cycles has been chosen to assure maximum data  
security. Instructions are initialised by two initial  
Coded cycles which unlock the Command Inter-  
face.Inaddition,for Erase,instructionconfirmation  
is again preceded by the two Coded cycles.  
Status Register Bits  
P/E.C.status is indicatedduring executionby Data  
Polling on DQ7, detection of Toggle on DQ6 and  
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.  
Any read attempt during Program or Erase com-  
mandexecutionwill automaticallyoutputthesefive  
StatusRegister bits. TheP/E.C. automaticallysets  
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits  
(DQ0, DQ1 and DQ4) are reserved for future use  
and should be masked. See Tables 9 and 10.  
8/29  
1...567891011...29

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