Datasheet > M29F002NT-120XK6TR

M29F002NT-120XK6TR

更新时间： 2024-01-07 04:04:10

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		闪存内存集成电路
页数	文件大小	规格书
29页	199K
描述
2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory

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M29F002NT-120XK6TR 技术参数

生命周期：	Transferred	零件包装代码：	QFJ
包装说明：	QCCJ,	针数：	32
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.36
最长访问时间：	120 ns	其他特性：	20 YEARS DATA RETENTION; 100000 PROGRAM/ERASE CYCLES
启动块：	TOP	数据保留时间-最小值：	20
JESD-30 代码：	R-PQCC-J32	长度：	13.995 mm
内存密度：	2097152 bit	内存集成电路类型：	FLASH
内存宽度：	8	功能数量：	1
端子数量：	32	字数：	262144 words
字数代码：	256000	工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	256KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
编程电压：	5 V	认证状态：	Not Qualified
座面最大高度：	3.56 mm	最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
类型：	NOR TYPE	宽度：	11.455 mm

M29F002NT-120XK6TR 数据手册

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M29F002T, M29F002NT, M29F002B

Instructions

impedance when the chip is deselected or the

outputs are disabled and when RPNC is at a Low

level.

Seven instructions are defined to perform Read

Array,Auto Select(to readthe ElectronicSignature

or Block ProtectionStatus), Program, BlockErase,

Chip Erase, Erase Suspend and Erase Resume.

The internal P/E.C. automatically handles all tim-

ing and verification of the Program and Erase

operations.The Status Register Data Polling, Tog-

gle, Error bits may be read at any time, during

programming or erase, to monitor the progress of

the operation.

Chip Enable (E). The Chip Enable input activates

the memory control logic, input buffers, decoders

andsenseamplifiers.E Highdeselectsthememory

andreducesthe powerconsumptiontothestandby

level. E can also be used to control writing to the

command register and to the memory array, while

Wremainsat a low level. TheChip Enablemust be

forced to V_IDduringthe Block Unprotection opera-

tion.

Instructions are composed of up to six cycles. The

first two cycles input a Coded sequence to the

CommandInterfacewhich iscommontoall instruc-

tions (see Table 8). The third cycle inputs the

instruction set-up command. Subsequent cycles

outputthe addressed data, Electronic Signatureor

Block Protection Status for Read operations. In

orderto giveadditionaldata protection,the instruc-

tions for Programand Block or Chip Erase require

furthercommandinputs. ForaPrograminstruction,

the fourth command cycle inputs the address and

data to be programmed. For an Erase instruction

(Block or Chip), the fourth and fifth cycles input a

further Coded sequence before the Erase confirm

command on the sixth cycle. Erasure of a memory

blockmaybe suspended,in orderto readdatafrom

anotherblock or to programdata in another block,

and then resumed.

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read

operation. When G is High the outputs are High

impedance. G must be forced to V_IDlevel during

Block Protection and Unprotection operations.

WriteEnable (W). This inputcontrols writing to the

CommandRegisterand Addressand Datalatches.

Reset/Block Temporary Unprotect/No Connect

Input (RPNC). The RPNC (not available for the

M29F002NT) input provides hardware reset and

protected block(s) temporary unprotection func-

tions. In read or write mode, the RPNC pin can be

left open (Not Connected) or held at V_IH. Reset of

the memory is acheived by pulling RPNC to V_ILfor

atleast 500ns.When the reset pulseis given,if the

memory is in Read or Standby modes, it will be

availablefor newoperationsin 50nsafter the rising

edge of RPNC. If the memory is in Erase, Erase

Suspend or Program modes the reset will take

10µs.Ahardwareresetduringan Eraseor Program

operation will corrupt the data being programmed

or the sector(s) being erased.

When power is first applied or if V_CCfalls below

V_LKO, the command interface is reset to Read

Array.

SIGNAL DESCRIPTIONS

Temporary block unprotection is made by holding

RPNC at V_ID. Inthis conditionpreviously protected

blocks can be programmed or erased. The transi-

tion of RPNC from V_IHto V_IDmust slower than

500ns. When RPNC is returnedfrom V_IDto V_IHall

blocks temporarily unprotected will be again pro-

tected.

See Figure 1 and Table1.

Address Inputs (A0-A17). The address inputs for

the memory array are latchedduring a write opera-

tion on the falling edge of Chip Enable E or Write

EnableW. When A9 is raisedto V_ID, eithera Read

ElectronicSignatureManufacturerorDeviceCode,

BlockProtectionStatus or a WriteBlock Protection

or Block Unprotectionis enableddependingon the

combinationof levelson A0, A1, A6, A12 and A15.

V_CCSupply Voltage. The power supply for all

operations (Read, Program and Erase).

V_SSGround. V_SSis the reference for all voltage

measurements.

Data Input/Outputs (DQ0-DQ7). Theinput is data

to be programmed in the memory array or a com-

mand to be written to the C.I. Both are latched on

the rising edge of Chip Enable E or Write Enable

W. The output is data from the Memory Array, the

Electronic Signature Manufacturer or Device

codes, the Block Protection Status or the Status

and DQ2, the Error bit DQ5 or the Erase Timer bit

DQ3. Outputs are valid when Chip Enable E and

Output Enable G are active. The output is high

DEVICE OPERATIONS

See Tables 4, 5 and 6.

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature,the Status Register or the BlockProtection

Status. Both Chip Enable E and Output Enable G

must be low in order to read the output of the

memory.

5/29

1 2 3 456 7 8...29

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