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M2066-13-670.8386 PDF预览

M2066-13-670.8386

更新时间: 2024-10-29 04:37:11
品牌 Logo 应用领域
艾迪悌 - IDT ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
12页 456K
描述
Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36

M2066-13-670.8386 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:QCCN,针数:36
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.3应用程序:SONET;SDH
JESD-30 代码:S-CQCC-N36JESD-609代码:e0
长度:8.99 mm功能数量:1
端子数量:36最高工作温度:70 °C
最低工作温度:封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:3.1 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:NO LEAD
端子节距:0.635 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.99 mm
Base Number Matches:1

M2066-13-670.8386 数据手册

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M2060/61/62, M2065/66/67  
Integrated  
Circuit  
Systems, Inc.  
VCSO FEC PLL FOR SONET/OTN  
P r e l i m i n a r y I n f o r m a t i o n  
External Loop Filter  
To provide stable PLL operation, the M2060/61/62 or  
M2065/66/67 requires use of an external loop filter. This  
is provided via the provided filter pins (see Figure 5).  
The loop filter is implemented as a differential circuit  
to minimize system noise interference.  
RLOOP CLOOP  
RPOST  
CPOST  
CPOST  
RLOOP CLOOP  
nOP_IN OP_OUT  
RPOST  
OP_IN  
nOP_OUT  
nVC  
VC  
4
9
8
5
6
7
Figure 5: External Loop Filter  
PLL bandwidth is affected by loop filter component  
values, “Mfec” and “Mfin” values, and the “PLL Loop  
Constants” listed in AC Characteristics on pg. 11.  
The FEC_SEL setting can be used to actively change PLL  
loop bandwidth in a given application. See “Mfec and  
Rfec Divider Look-Up Tables (LUTs)” on pg. 3.  
See Table 10, Example Values for Loop Filter External  
Components, on pg. 8.  
PLL Simulator Tool Available  
A free PC software utility is available on the ICS website  
(www.icst.com). The M2000 Timing Modules PLL  
Simulator is a downloadable application that simulates  
PLL jitter and wander transfer characteristics. This  
enables the user to set appropriate external loop  
component values in a given application.  
1
Example Values for Loop Filter External Components  
for Particular M206x Series Devices  
VCSO Parameters: K  
= 800kHz/V, R = 100k  
(pin NBW = 0), VCSO Bandwidth = 700kHz.  
VCO  
IN  
Device  
Device Configuration  
Example External Component Values  
Nominal Performance With These Values  
FIN_SEL MRSEL  
1:0  
FRef  
FVCSO  
R loop  
C loop  
R post  
C post  
PLL Loop Damping Passband  
1:0  
Bandwidth Factor Peaking(dB)  
(MHz)  
(MHz)  
M2060, M2060 622.08 622.08  
1 1  
0 1  
6.5  
5.9  
6.5  
6.5  
0.05  
0.06  
0.05  
0.05  
5.6kΩ  
243.0kΩ  
8.2kΩ  
10µF  
0.1µF  
10µF  
10µF  
68kΩ  
34kΩ  
100kΩ  
100kΩ  
470pF  
470pF  
470pF  
470pF  
530Hz  
1kHz  
M2060, M2065 155.52 669.3266 1 0  
1 0 0  
0 1  
M2061, M2066 77.76 622.08  
M2061  
0 1  
0 0  
360Hz  
19.44 622.08  
1 1  
8.2kΩ  
360Hz  
Table 10: Example Values for Loop Filter External Components  
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and  
Passband Peaking. For PLL Simulator software, go to www.icst.com.  
Refer to the M206x Series product web page at  
www.icst.com/products/summary/m2060-2067.htm  
for additional product information.  
M2060/61/62 M2065/66/67 Datasheet Rev 0.4  
8 of 12  
Revised 30Jul2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  

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