Datasheet > M2004-32-622.0800

M2004-32-622.0800

更新时间： 2024-11-30 04:39:27

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
10页	403K
描述
PLL Based Clock Driver, 2004 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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P r e l i m i n a r y I n f o r m a t i o n

Integrated

Circuit

Systems, Inc.

M2004-x2

FREQUENCY TRANSLATION PLL FAMILY

GENERAL DESCRIPTION

The M2004 variants -22, -32, -42, and -52 are VCSO

(Voltage Controlled SAW Oscillator)

PIN ASSIGNMENT (9 x 9 mm SMT)

based clock generator PLLs

designed for clock frequency

translation and jitter attenuation in

a high-speed data communications

system. The clock multiplication

ratio and output divider ratio are

VCC

DNC

nFOUT

FOUT

GND

M2004-x2

pin selectable. External loop components allow the

tailoring of PLL loop response. Based on the M2004-02,

these device variants add the Hitless Switching with

Phase Build-out (HS/PBO) feature. HS/PBO ensures

that reference clock reselection does not disrupt the

output clock. In addition, a fixed Narrow Loop

Bandwidth feature (Fixed NBW) is included in the some

of the device variants.

( T o p V i e w )

VCC

GND

FEATURES

Figure 1: Pin Assignment

◆ Pin-compatible with M2004-02/-12, these new product

Example Input / Output Frequency Combinations

Input (MHz) VCSO ** (MHz) Output (MHz) Application

variants offer new functions

◆ Hitless Switching with Phase Build-out to ensure

SONET/SDH MTIE and TDEV compliance during

reference clock reselection

19.44

77.76

155.52

77.76

311.04

622.08

OC-12 / 48

/192

622.08

Table 1: Example Input / Output Frequency Combinations

Device Variants and Corresponding Functions

◆ Fixed Narrow Loop Bandwidth feature available

◆ Ideal for OC-48/192 data clock

Hitless Switching /

Phase Build-out Triggered by

Phase Transient Mux Reselection

Fixed

NBW

◆ Integrated SAW (surface acoustic wave) delay line

◆ VCSO frequency from 300 to 700MHz ^**

Variant

M2004-02

M2004-12

M2004-22

M2004-32

M2004-42

M2004-52

✓ Yes

◆ Low phase jitter of < 0.5ps rms, typical

(12kHz to 20MHz or 50kHz to 80MHz)

◆ Pin-selectable configuration

◆ Reference clock inputs support differential LVDS,

LVPECL, as well as single-ended LVCMOS, LVTTL

✓ Yes

Table 2: Device Variants and Corresponding Functions

◆ Industrial temperature available

◆ Single 3.3V power supply

* This sheet covers only parts numbered M2004-22, -32, -42, -52.

See M2004-02/-12 Product Data Sheet for M2004-02 & M2004-12.

** Specify VCSO center frequency at time of order.

◆ Small 9 x 9 mm SMT (surface mount) package

SIMPLIFIED BLOCK DIAGRAM

Loop

Filter

M2004-x2

DIF_REF

nDIF_REF

VCSO

REF_CLK

REF_SEL

M Divider

FOUT

N Divider

nFOUT

M5:0

N1:0

Figure 2: Simplified Block Diagram

M2004-x2 Datasheet Rev 1.3

Revised 10Sep2003

M2004-x2 Frequency Translation PLL Family

Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400

12 3 4 5 6 7...10

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与M2004-32-622.0800相关器件

型号	品牌	获取价格	描述	数据表
M2004-32-622.0800LF	IDT	获取价格	PLL Based Clock Driver, 2004 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9
M2004-32I622.0800	IDT	获取价格	PLL Based Clock Driver, 2004 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9
M2004-32I622.0800LF	IDT	获取价格	PLL Based Clock Driver, 2004 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9
M2004-42-622.0800LF	IDT	获取价格	PLL Based Clock Driver, 2004 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9
M2004-51-622.0800LF	IDT	获取价格	PLL Based Clock Driver, 1 True Output(s), 1 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC,
M2004-51I622.0800	IDT	获取价格	PLL Based Clock Driver, 1 True Output(s), 1 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC,
M2004S036 70.656000	MTRONPTI	获取价格
M2004S037 70.656000	MTRONPTI	获取价格
M2005-01-622.0800	IDT	获取价格	Support Circuit, 1-Func, 9 X 9 MM, SMT-36
M2005-01-625.0000	IDT	获取价格	Support Circuit, 1-Func, 9 X 9 MM, SMT-36

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