Datasheet > M2005-02-625.0000

M2005-02-625.0000

更新时间： 2024-11-29 21:00:55

品牌	Logo	应用领域
SPECTRUM		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
10页	1345K
描述
Support Circuit, 1-Func,

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M2005-02-625.0000 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	QCCN,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.91	应用程序：	SONET;SDH
JESD-30 代码：	S-XQCC-N36	长度：	9 mm
功能数量：	1	端子数量：	36
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	UNSPECIFIED	封装代码：	QCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	2.8 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	COMMERCIAL	端子形式：	NO LEAD
端子节距：	0.635 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	9 mm
Base Number Matches：	1

M2005-02-625.0000 数据手册

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M2005-02

Micro Networks

An Integrated Circuit Systems Company

Preliminary Specifications

M2005-02

Frequency Translator

DESCRIPTION

The M2005-02 integrates a high performance Phase

Locked Loop (PLL) with a Voltage Controlled SAW

Oscillator (VCSO) to provide a low jitter Frequency

Synthesizer in a 9mm x 9mm surface mount

package.

The internal high “Q” SAW filter provides low jitter

signal performance and determines the maximum

output frequency of the VCSO. A programmable

output divider can divide the VCSO frequency by a

factor of 4 to achieve an output as low as 77.76MHz

with a 311.04MHz VCSO.

The input to the Frequency Synthesizer is provided

by selecting between one of two input reference

clocks. The maximum input frequency is 250 MHz.

FEATURES

Output Clock Frequency up to 700MHz

Differential LVPECL Outputs

Serial control of the input divider, the feedback

divider, and output divider is provided via the

configuration logic.

Internal Low-jitter SAW-based Oscillator

Intrinsic Jitter <1ps rms (12kHz - 20MHz)

Jitter Attenuation of Input Reference Clock

Dual Input MUX

An external loop filter sets the PLL bandwidth which

can be optimized to provide jitter attenuation of the

input reference clock.

A HOLD feature freezes the VCSO frequency so that

a stable output clock can be maintained when both

input reference clocks are lost.

Configurable Loop and Output Dividers

Tunable Loop Filter Response

Single 3.3V Supply

The bandwidth control, low phase noise, and HOLD

features make the M2005-02 ideal for use as a clock

jitter attenuator, frequency translator, and clock

frequency generator in OC-3 through OC-192

applications.

Small 9mm x 9mm SMT Package

HOLD Mode During Loss of Input

Reference Clock

APPLICATIONS

ABSOLUTE MAX RATINGS

Inputs, V_I:

................................................. -0.5 to V_CC+0.5V

SONET / SDH / 10GbE System

Synchronization

Output, V_O: ................................................. -0.5 to V_CC+0.5V

Supply Voltage, V_CC: ......................................................... 4.6 V

Storage Temperature, T_STO:............................ -45°C to +100°C

Add / Drop Muxes, Access and Edge

Switches

Stresses beyond those listed under Absolute Maximum Ratings may cause

permanent damage to the device. These ratings are stress specifications

only. Functional operation of product at these conditions or any conditions

beyond those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for extended peri-

ods may affect product reliability.

Line Card System Clock Cleaner /

Translator

Optical Module Clock Cleaner / Translator

ISO 9001

Registered

Micro Networks

324 Clark Street

Worcester, MA 01606

tel: 508-852-5400

fax: 508-852-8456

www.micronetworks.com

12 3 4 5 6 7...10

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