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M2004-02I400.0000T PDF预览

M2004-02I400.0000T

更新时间: 2024-11-29 20:06:51
品牌 Logo 应用领域
艾迪悌 - IDT ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
10页 162K
描述
CLCC-36, Reel

M2004-02I400.0000T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:CLCC
包装说明:,针数:36
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.82电信集成电路类型:ATM/SONET/SDH SUPPORT CIRCUIT
Base Number Matches:1

M2004-02I400.0000T 数据手册

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P r o d u c t D a t a S h e e t  
Integrated  
Circuit  
Systems, Inc.  
M2004-02/-12  
FREQUENCY TRANSLATION PLL  
GENERAL DESCRIPTION  
PIN ASSIGNMENT (9 x 9 mm SMT)  
The M2004 variants -02 and -12 are VCSO (Voltage  
Controlled SAW Oscillator) based  
clock generator PLLs designed for  
clock frequency translation and jitter  
attenuation in a high-speed data  
communications system. The clock  
multiplication ratio and output  
divider ratio are pin selectable.  
M1  
M2  
M3  
M4  
M5  
VCC  
DNC  
DNC  
DNC  
NC  
28  
29  
30  
31  
32  
33  
34  
35  
36  
18  
17  
16  
15  
14  
13  
12  
11  
10  
MR  
nFOUT  
FOUT  
GND  
N1  
M2004-02  
M2004-12  
External loop components allow the tailoring of PLL  
loop response. The M2004-12 adds Hitless Switching  
with Phase Build-out (HS/PBO) to ensure that reference  
clock reselection does not disrupt the output clock.  
( T o p V i e w )  
N0  
VCC  
GND  
Also read about device variants -22, -32, -42, and  
-52 in the M2004-x2 Preliminary Information sheet.  
FEATURES  
Ideal for OC-48/192 data clock  
Integrated SAW (surface acoustic wave) delay line  
Figure 1: Pin Assignment  
Example Input / Output Frequency Combinations  
VCSO frequency from 300 to 700MHz  
(Specify VCSO center frequency at time of order)  
Input Clock VCSO 1  
Output  
Application  
Low phase jitter of < 0.5ps rms, typical (12kHz to  
20MHz or 50kHz to 80MHz)  
(MHz)  
Freq (MHz) Freq (MHz)  
19.44  
77.76  
Pin-selectable configuration  
38.80  
77.76  
155.52  
25.00  
155.52  
622.08  
The M2004-12 adds Hitless Switching with Phase  
Build-out (HS/PBO) to ensure SONET/SDH MTIE and  
TDEV compliance during reference clock reselection  
OC-12 / 48 /192  
Gigabit Ethernet  
311.04  
622.08  
Reference clock inputs support differential LVDS,  
LVPECL, as well as single-ended LVCMOS, LVTTL  
625.00  
156.25  
Table 1: Example Input / Output Frequency Combinations  
Industrial temperature available  
Single 3.3V power supply  
Note 1: Specify VCSO center frequency at time of order  
Small 9 x 9 mm SMT (surface mount) package  
SIMPLIFIED BLOCK DIAGRAM  
Loop  
Filter  
M2004-02/-12  
DIF_REF  
0
nDIF_REF  
VCSO  
REF_CLK  
REF_SEL  
1
M Divider  
FOUT  
N Divider  
nFOUT  
6
2
M5:0  
N1:0  
MR  
Figure 2: Simplified Block Diagram  
M2004-02/-12 Datasheet Rev 1.3  
Revised 17Dec2004  
M2004-02/-12 Frequency Translation PLL  
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400  

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