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M1A3PE3000L-1FGG896M PDF预览

M1A3PE3000L-1FGG896M

更新时间： 2024-11-10 15:46:43
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟栅可编程逻辑
页数 文件大小 规格书
216页 10845K
描述
Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 250MHz, 75264-Cell, CMOS, PBGA896, 1 MM PITCH, GREEN, FBGA-896

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M1A3PE3000L-1FGG896M 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：BGA, BGA896,30X30,40Reach Compliance Code：compliant
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.31最大时钟频率：250 MHz
JESD-30 代码：S-PBGA-B896JESD-609代码：e1
长度：31 mm湿度敏感等级：3
可配置逻辑块数量：75264等效关口数量：3000000
输入次数：620逻辑单元数量：75264
输出次数：620端子数量：896
最高工作温度：125 °C最低工作温度：-55 °C
组织：75264 CLBS, 3000000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA896,30X30,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：250电源：1.2/1.5,1.2/3.3 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：2.44 mm子类别：Field Programmable Gate Arrays
最大供电电压：1.575 V最小供电电压：1.14 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：31 mm
Base Number Matches：1

M1A3PE3000L-1FGG896M 数据手册

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Revision 5  
Military ProASIC3/EL Low Power Flash FPGAs  
with Flash*Freeze Technology  
•
Architecture Supports Ultra-High Utilization  
Features and Benefits  
Advanced and Pro (Professional) I/Os††  
Military Temperature Tested and Qualified  
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os  
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages—up to 8 Banks per Chip  
†
•
Each Device Tested from –55°C to 125°C  
Firm-Error Immune  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and  
•
Not Susceptible to Neutron-Induced Configuration Loss  
†
Low Power  
LVCMOS 2.5 V / 5.0 V Input  
•
•
•
Dramatic Reduction in Dynamic and Static Power  
1.2 V to 1.5 V Core and I/O Voltage Support for Low Power  
•
•
Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS  
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL  
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3  
Class I and II (A3PE3000L only)  
†
Low Power Consumption in Flash*Freeze Mode Allows for  
Instantaneous Entry To / Exit From Low-Power Flash*Freeze  
ƒ
Mode  
•
•
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths  
Hot-Swappable and Cold-Sparing I/Os  
Programmable Output Slew Rate and Drive Strength  
Programmable Input Delay (A3PE3000L only)  
Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)  
Weak Pull-Up/-Down  
•
•
Supports Single-Voltage System Operation  
Low-Impedance Switches  
High Capacity  
•
•
•
250K to 3M System Gates  
Up to 504 Kbits of True Dual-Port SRAM  
Up to 620 User I/Os  
IEEE 1149.1 (JTAG) Boundary Scan Test  
Pin-Compatible Packages across the Military ProASIC 3EL Family  
®
Reprogrammable Flash Technology  
Clock Conditioning Circuit (CCC) and PLL  
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process  
Live-at-Power-Up (LAPU) Level 0 Support  
Single-Chip Solution  
•
•
•
Six CCC Blocks—One Block with Integrated PLL in ProASIC3  
and All Blocks with Integrated PLL in ProASIC3EL  
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,  
and External Feedback  
Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V  
systems) and 350 MHz (1.5 V systems)  
Retains Programmed Design when Powered Off  
High Performance  
•
350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System  
Performance  
3.3 V, 66 MHz, 64-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit  
PCI (1.2 V systems)  
SRAMs and FIFOs  
•
•
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,  
and ×18 organizations available)  
True Dual-Port SRAM (except ×18)  
24 SRAM and FIFO Configurations with Synchronous  
Operation:  
– 250 MHz: For 1.2 V Systems  
– 350 MHz: For 1.5 V Systems  
In-System Programming (ISP) and Security  
•
•
•
Secure ISP Using On-Chip 128-Bit Advanced Encryption  
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)  
®
•
FlashLock to Secure FPGA Contents  
High-Performance Routing Hierarchy  
ARM® Processor Support in ProASIC3/EL FPGAs  
•
•
•
Segmented, Hierarchical Routing and Clock Structure  
High-Performance, Low-Skew Global Network  
ARM Cortex™-M1 Soft Processor Available with or without  
Debug  
Table 1 • Military ProASIC3/EL Low-Power Devices  
ProASIC3/EL Devices  
ARM Cortex-M1 Devices  
System Gates  
A3P250  
A3PE600L  
A3P1000  
A3PE3000L  
1
M1A3P1000  
M1A3PE3000L  
250,000  
600,000  
13,824  
108  
24  
1M  
24,576  
144  
32  
3M  
75,264  
504  
112  
1
VersaTiles (D-flip-flops)  
RAM kbits (1,024 bits)  
4,608-Bit Blocks  
6,144  
36  
8
FlashROM Kbits  
1
1
1
2
Secure (AES) ISP  
Yes  
1
Yes  
6
Yes  
1
Yes  
6
Integrated PLL in CCCs  
VersaNet Globals  
I/O Banks  
18  
4
18  
18  
18  
8
4
8
Maximum User I/Os  
68  
270  
154  
620  
Package Pins  
VQFP  
VQ100  
PQFP  
PQ208  
FG144, FG256, FG484  
FBGA  
FG484  
FG484, FG896  
Notes:  
1. Refer to the Cortex-M1 product brief for more information.  
2. AES is not available for ARM-enabled ProASIC3/EL devices.  
† A3P250 and A3P1000 support only 1.5 V core operation.  
ƒ Flash*Freeze technology is not available for A3P250 or A3P1000.  
††Pro I/Os are not available on A3P250 or A3P1000.  
September 2014  
I
© 2014 Microsemi Corporation  
 
 
 
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M1A3PE3000L-1FGG896Y MICROSEMI

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M1A3PE3000L-1FGG896YI MICROSEMI

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 		Military ProASIC3/EL Low-Power Flash FPGAs
M1A3PE3000L-1PQG208 MICROSEMI

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 		Field Programmable Gate Array, 250MHz, 75264-Cell, CMOS, PQFP208,
M1A3PE3000L-1PQG208YI MICROSEMI

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 		Field Programmable Gate Array, 250MHz, 75264-Cell, CMOS, PQFP208,

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