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M1A3PE3000-FG896

更新时间： 2024-11-08 05:44:35

品牌	Logo	应用领域
ACTEL		现场可编程门阵列闪存可编程逻辑栅时钟
页数	文件大小	规格书
152页	5016K
描述
ProASIC3E Flash Family FPGAs

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技术参数
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M1A3PE3000-FG896 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	31 X 31 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-896	Reach Compliance Code：	compliant
风险等级：	5.82	Is Samacsys：	N
最大时钟频率：	350 MHz	JESD-30 代码：	S-PBGA-B896
JESD-609代码：	e0	长度：	31 mm
湿度敏感等级：	3	可配置逻辑块数量：	75264
等效关口数量：	3000000	输入次数：	620
逻辑单元数量：	75264	输出次数：	620
端子数量：	896	最高工作温度：	70 °C
最低工作温度：		组织：	75264 CLBS, 3000000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA896,30X30,40	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	225
电源：	1.5/3.3 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	2.44 mm
子类别：	Field Programmable Gate Arrays	最大供电电压：	1.575 V
最小供电电压：	1.425 V	标称供电电压：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	31 mm	Base Number Matches：	1

M1A3PE3000-FG896 数据手册

v1.0

ProASIC3E Flash Family FPGAs

with Optional Soft ARM Support

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

Features and Benefits

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS

2.5 V / 5.0 V Input

High Capacity

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay

• Retains Programmed Design when Powered Off

On-Chip User Nonvolatile Memory

H^•igh^{1 k}P^be^itr^of^fo^Fr^lm^asha^Rn^Oc^Me^{with Synchronous Interfacing}

• Schmitt Trigger Option on Single-Ended Inputs

• Weak Pull-Up/-Down

• 350 MHz System Performance

• IEEE 1149.1 (JTAG) Boundary Scan Test

• 3.3 V, 66 MHz 64-Bit PCI

• Pin-Compatible Packages across the ProASIC 3E Family

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, Each with an Integrated PLL

• Configurable

Phase-Shift,

Multiply/Divide,

Delay

• FlashLock to Secure FPGA Contents

Capabilities and External Feedback

Low Power

• Wide Input Frequency Range (1.5 MHz to 200 MHz)

• Core Voltage for Low Power

• Support for 1.5-V-Only Systems

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

H^•igh^Lo-^wPe^-Imrf^po^er^dm^ana^cen^Fc^le^ashRo^Swuⁱt^tcin^heg^sHierarchy

• Segmented, Hierarchical Routing and Clock Structure

• Ultra-Fast Local and Long-Line Network

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

Operation up to 350 MHz

• Enhanced High-Speed, Very-Long-Line Network

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

ARM^®Processor Support in ProASIC3E FPGAs

• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available

with or without Debug

Pro (Professional) I/O

• 700 Mbps DDR, LVDS-Capable I/Os

Table 1-1 • ProASIC3E Product Family

ProASIC3E Devices

Cortex-M1 Devices

System Gates

A3PE600

A3PE1500

A3PE3000

M1A3PE1500

M1A3PE3000

600 k

13,824

108

1.5 M

38,400

270

3 M

75,264

504

112

1 k

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

1 k

Secure (AES) ISP

Yes

CCCs with Integrated PLLs

VersaNet Globals

I/O Banks

Maximum User I/Os

270

444

620

Package Pins

PQFP

FBGA

PQ208

FG256, FG484

PQ208

FG484, FG676

PQ208

FG324, FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. The PQ208 package has six CCCs and two PLLs.

3. Six chip (main) and three quadrant global networks are available.

4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs handbook.

March 2008

12 3 4 5 6 7...152

中文翻译

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与M1A3PE3000-FG896相关器件

型号	品牌	获取价格	描述	数据表
M1A3PE3000-FG896ES	ACTEL	获取价格	ProASIC3E Flash Family FPGAs
M1A3PE3000-FG896I	ACTEL	获取价格	ProASIC3E Flash Family FPGAs
M1A3PE3000-FG896I	MICROSEMI	获取价格	Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 350MHz, 75264-Cell, CMOS, PBGA89
M1A3PE3000-FG896PP	ACTEL	获取价格	ProASIC3E Flash Family FPGAs
M1A3PE3000-FG896Y	MICROSEMI	获取价格	Field Programmable Gate Array, 350MHz, 75264-Cell, CMOS, PBGA896
M1A3PE3000-FG896YI	MICROSEMI	获取价格	Field Programmable Gate Array, 350MHz, 75264-Cell, CMOS, PBGA896
M1A3PE3000-FGG324	ACTEL	获取价格	Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 350MHz, 75264-Cell, CMOS, PBGA32
M1A3PE3000-FGG324	MICROSEMI	获取价格	Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 350MHz, 75264-Cell, CMOS, PBGA32
M1A3PE3000-FGG324I	ACTEL	获取价格	Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 350MHz, 75264-Cell, CMOS, PBGA32
M1A3PE3000-FGG324I	MICROSEMI	获取价格	Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 350MHz, 75264-Cell, CMOS, PBGA32

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