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M1A3P400-1FG144I

更新时间： 2024-11-12 05:44:35

品牌	Logo	应用领域
ACTEL		可编程逻辑
页数	文件大小	规格书
206页	5922K
描述
ProASIC3 Flash Family FPGAs

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技术参数
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M1A3P400-1FG144I 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	13X 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, FBGA-144	Reach Compliance Code：	compliant
风险等级：	5.83	最大时钟频率：	350 MHz
JESD-30 代码：	S-PBGA-B144	JESD-609代码：	e0
长度：	13 mm	湿度敏感等级：	3
可配置逻辑块数量：	9216	等效关口数量：	400000
输入次数：	97	逻辑单元数量：	9216
输出次数：	97	端子数量：	144
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	9216 CLBS, 400000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA144,12X12,40
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	225	电源：	1.5/3.3 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.55 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	1.575 V	最小供电电压：	1.425 V
标称供电电压：	1.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD SILVER	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	13 mm
Base Number Matches：	1

M1A3P400-1FG144I 数据手册

v1.0

ProASIC3 Flash Family FPGAs

with Optional Soft ARM Support

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

Features and Benefits

• 15 k to 1 M System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

High Capacity

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

†

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS

2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS (A3P250 and above)

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• I/O Registers on Input, Output, and Enable Paths

‡

• Hot-Swappable and Cold Sparing I/Os

†

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• Retains Programmed Design when Powered Off

High Performance

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

Clock Conditioning Circuit (CCC) and PLL^†

• Six CCC Blocks, One with an Integrated PLL

• 350 MHz System Performance

†

• 3.3 V, 66 MHz 64-Bit PCI

In-System Programming (ISP) and Security

• Configurable

Phase-Shift,

Multiply/Divide,

Delay

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Embedded Memory^†

Standard (AES) Decryption (except ARM-enabled ProASIC 3

†

devices) via JTAG (IEEE 1532–compliant)

• FlashLock to Secure FPGA Contents

• 1 kbit of FlashROM User Nonvolatile Memory

Low Power

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

• Core Voltage for Low Power

†

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

• Support for 1.5 V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/O

• True Dual-Port SRAM (except ×18)

ARM Processor Support in ProASIC3 FPGAs

• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft

Processor Available with or without Debug

• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

ProASIC3 Product Family

ProASIC3 Devices

A3P015 A3P030 A3P060 A3P125

A3P250

A3P400

A3P600

A3P1000

ARM7 Devices

M7A3P1000

Cortex-M1 Devices

System Gates

M1A3P250

M1A3P400

M1A3P600

M1A3P1000

15 k

128

384

–

30 k

256

768

–

60 k

512

1,536

125 k

1,024

3,072

250 k

–

400 k

–

600 k

–

1 M

–

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

6,144

9,216

13,824

108

24,576

144

–

FlashROM Bits

1 k

–

1 k

–

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

Secure (AES) ISP

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

133

157

194

235

300

Package Pins

QFN

QN68

QN132 QN132 QN132

QN132

VQFP

VQ100

TQ144

VQ100

TQ144

PQ208

VQ100

TQFP

PQFP

PQ208

FG144 FG144/256

PQ208

FG144/256/

484

PQ208

FG144/256/

484

PQ208

FG144/256/

484

FBGA

FG144

Notes:

1. Refer to the CoreMP7 datasheet or Cortex-M1 product brief for more information.

2. AES is not available for ARM-enabled ProASIC3 devices.

3. Six chip (main) and three quadrant global networks are available for A3P060 and above.

4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs handbook.

5. The M1A3P250 device does not support this package.

†

A3P015 and A3P030 devices do not support this feature.

‡ Supported only by A3P015 and A3P030 devices.

February 2008

12 3 4 5 6 7...206

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与M1A3P400-1FG144I相关器件

型号	品牌	获取价格	描述	数据表
M1A3P400-1FG144IY	MICROSEMI	获取价格	Field Programmable Gate Array,
M1A3P400-1FG144PP	ACTEL	获取价格	ProASIC3 Flash Family FPGAs
M1A3P400-1FG144Y	MICROSEMI	获取价格	Field Programmable Gate Array, 9216 CLBs, 400000 Gates, CMOS, PBGA144, 13 X 13 MM, 1.45 MM
M1A3P400-1FG144YI	MICROSEMI	获取价格	Field Programmable Gate Array, 9216 CLBs, 400000 Gates, CMOS, PBGA144, 13 X 13 MM, 1.45 MM
M1A3P400-1FG256	MICROSEMI	获取价格	Field Programmable Gate Array, 9216 CLBs, 400000 Gates, 350MHz, CMOS, PBGA256, 17 X 17 MM,
M1A3P400-1FG256I	MICROSEMI	获取价格	Field Programmable Gate Array, 9216 CLBs, 400000 Gates, CMOS, PBGA256, 17 X 17 MM, 1.60 MM
M1A3P400-1FG256IY	MICROSEMI	获取价格	Field Programmable Gate Array
M1A3P400-1FG256Y	MICROSEMI	获取价格	Field Programmable Gate Array, 9216 CLBs, 400000 Gates, CMOS, PBGA256
M1A3P400-1FG484I	MICROSEMI	获取价格	Field Programmable Gate Array, 9216 CLBs, 400000 Gates, CMOS, PBGA484, 23 X 23 MM, 2.23 MM
M1A3P400-1FG484IY	MICROSEMI	获取价格	Field Programmable Gate Array

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