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M100LVEP111FATW PDF预览

M100LVEP111FATW

更新时间: 2024-02-24 17:22:07
品牌 Logo 应用领域
安森美 - ONSEMI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
13页 168K
描述
100LVE SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LQFP-32

M100LVEP111FATW 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP-32
针数:32Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.73
其他特性:NECL MODE OPERATING RANGE: VCC = 0V WITH VEE = -2.375V TO -3.8V系列:100LVE
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:2
功能数量:1反相输出次数:
端子数量:32实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):0.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.025 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.8 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

M100LVEP111FATW 数据手册

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MC100LVEP111  
2.5V / 3.3V 1:10 Differential  
ECL/PECL/HSTL Clock Driver  
Description  
The MC100LVEP111 is a low skew 1to10 differential driver,  
designed with clock distribution in mind, accepting two clock sources into  
an input multiplexer. The PECL input signals can be either differential or  
http://onsemi.com  
MARKING  
singleended (if the V output is used). HSTL inputs can be used when  
BB  
the LVEP111 is operating under PECL conditions.  
DIAGRAMS*  
The LVEP111 specifically guarantees low outputtooutput skew.  
Optimal design, layout, and processing minimize skew within a device and  
from device to device.  
To ensure tightest skew, both sides of differential outputs identically  
terminate into 50 W even if only one output is being used. If an output  
pair is unused, both outputs may be left open (unterminated) without  
affecting skew.  
MC100  
LVEP111  
AWLYYWWG  
LQFP32  
FA SUFFIX  
CASE 873A  
32  
The MC100LVEP111, as with most other ECL devices, can be  
1
operated from a positive V supply in PECL mode. This allows the  
CC  
LVEP111 to be used for high performance clock distribution in +3.3 V or  
+2.5 V systems. Singleended CLK input operation is limited to a V  
CC  
1
3.0 V in PECL mode, or V v 3.0 V in NECL mode when using VBB  
EE  
MC100  
LVEP111  
AWLYYWW  
G
32  
1
(See Figure 11). Full operating range is available when using an external  
voltage reference (See Figure 10). Designers can take advantage of the  
LVEP111’s performance to distribute low skew clocks across the  
backplane or the board.  
QFN32  
MN SUFFIX  
CASE 488AM  
Features  
A
= Assembly Location  
= Wafer Lot  
= Year  
WL  
YY  
WW  
85 ps Typical DevicetoDevice Skew  
20 ps Typical OutputtoOutput Skew  
= Work Week  
G or G = PbFree Package  
*For additional marking information, refer to  
Application Note AND8002/D.  
Jitter Less than 1 ps RMS  
Maximum Frequency > 3 GHz Typical  
V Output  
BB  
430 ps Typical Propagation Delay  
The 100 Series Contains Temperature Compensation  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 10 of this data sheet.  
PECL and HSTL Mode Operating Range: V = 2.375 V to 3.8 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
with V = 2.375 V to 3.8 V  
EE  
Open Input Default State  
LVDS Input Compatible  
Fully Compatible with MC100EP111  
PbFree Packages are Available  
© Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
October, 2012 Rev. 20  
MC100LVEP111/D  

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