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M1010-01I156.2500 PDF预览

M1010-01I156.2500

更新时间: 2024-09-26 05:44:27
品牌 Logo 应用领域
矽成 - ICSI 衰减器时钟
页数 文件大小 规格书
8页 355K
描述
VCSO BASED CLOCK JITTER ATTENUATOR

M1010-01I156.2500 数据手册

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P r e l i m i n a r y I n f o r m a t i o n  
Integrated  
Circuit  
Systems, Inc.  
M1010-01  
VCSO BASED CLOCK JITTER ATTENUATOR  
GENERAL DESCRIPTION  
PIN ASSIGNMENT (9 x 9 mm SMT)  
The M1010-01 is a VCSO (Voltage Controlled SAW  
Oscillator) based clock jitter  
attenuator PLL designed for clock  
jitter attenuation and frequency  
translation. The device is ideal for  
generating the transmit reference  
clock for OC-12 and OC-48 optical  
network systems supporting 622 -  
FIN_SEL0  
SEL0  
SEL1  
SEL2  
NC  
VCC  
NC  
nFOUT  
FOUT  
GND  
NC  
28  
29  
30  
31  
18  
17  
16  
15  
14  
13  
12  
11  
10  
M1010  
2,488 MHz rates. It can serve to jitter attenuate a  
stratum reference clock or a recovered clock in loop  
timing mode. The M1010-01 module includes a  
proprietary SAW (surface acoustic wave) delay line as  
part of the VCSO. This results in a high frequency,  
high-Q, low phase noise oscillator that assures low  
intrinsic output jitter.  
32  
33  
34  
35  
36  
VCC  
( T o p V i e w )  
DNC  
DNC  
NC  
VCC  
GND  
DNC  
FEATURES  
Ideal for OC-12/48 data clock  
Figure 1: Pin Assignment  
Integrated SAW delay line  
Example I/O Clock Frequency Combinations  
Using M1010-01-155.5200  
Output frequencies from 150 to 175 MHz  
(Specify VCSO output frequency at time of order)  
Input Reference  
Clock  
Frequency  
Input (Mfin)  
Ratio  
Output  
Clock MHz  
Low phase jitter of 0.5 ps rms, typical (12kHz to 20MHz)  
LVPECL clock output  
(MHz)  
8
2
1
19.44  
77.76  
155.52  
Pin-selectable feedback and reference divider ratios,  
no programming required  
155.52  
Scalable dividers provide further adjustment of loop  
bandwidth as well as jitter tolerance  
Table 1: Example I/O Clock Frequency Combinations  
Reference clock inputs support differential LVDS,  
LVPECL, as well as single-ended LVCMOS, LVTTL  
Single 3.3V power supply  
Small 9 x 9 mm SMT (surface mount) package  
SIMPLIFIED BLOCK DIAGRAM  
Loop  
Filter  
M1010  
DIF_REF0  
0
nDIF_REF0  
R Div  
VCSO  
DIF_REF1  
1
nDIF_REF1  
M Div  
Mfin Div  
REF_SEL  
3
2
FOUT  
SEL2:0  
Divider LUT  
nFOUT  
Mfin Divider  
LUT  
FIN_SEL1:0  
Figure 2: Simplified Block Diagram  
M1010-01 Datasheet Rev 0.4  
Revised 29Sep2003  
M1010-01 VCSO Based Clock Jitter Attenuator  
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400  

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