Datasheet > M1010-01-155.5200LF

M1010-01-155.5200LF

更新时间： 2024-02-18 12:59:39

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
8页	154K
描述
PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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M1010-01-155.5200LF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCN,	针数：	36
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.76	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-CQCC-N36	JESD-609代码：	e3
长度：	8.99 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	36	实输出次数：	1
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	3.1 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.635 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	8.99 mm
最小 fmax：	175 MHz	Base Number Matches：	1

M1010-01-155.5200LF 数据手册

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P r e l i m i n a r y I n f o r m a t i o n

Integrated

Circuit

Systems, Inc.

M1010-01

VCSO BASED CLOCK JITTER ATTENUATOR

GENERAL DESCRIPTION

PIN ASSIGNMENT (9 x 9 mm SMT)

The M1010-01 is a VCSO (Voltage Controlled SAW

Oscillator) based clock jitter

attenuator PLL designed for clock

jitter attenuation and frequency

translation. The device is ideal for

generating the transmit reference

clock for OC-12 and OC-48 optical

network systems supporting 622 -

FIN_SEL0

SEL0

SEL1

SEL2

VCC

nFOUT

FOUT

GND

M1010

2,488 MHz rates. It can serve to jitter attenuate a

stratum reference clock or a recovered clock in loop

timing mode. The M1010-01 module includes a

proprietary SAW (surface acoustic wave) delay line as

part of the VCSO. This results in a high frequency,

high-Q, low phase noise oscillator that assures low

intrinsic output jitter.

VCC

( T o p V i e w )

DNC

VCC

GND

DNC

FEATURES

◆ Ideal for OC-12/48 data clock

Figure 1: Pin Assignment

◆ Integrated SAW delay line

Example I/O Clock Frequency Combinations

Using M1010-01-155.5200

◆ Output frequencies from 150 to 175 MHz

(Specify VCSO output frequency at time of order)

Input Reference

Clock

Frequency

Input (Mfin)

Ratio

Output

Clock MHz

◆ Low phase jitter of 0.5 ps rms, typical (12kHz to 20MHz)

◆ LVPECL clock output

(MHz)

19.44

77.76

155.52

◆ Pin-selectable feedback and reference divider ratios,

no programming required

155.52

◆ Scalable dividers provide further adjustment of loop

bandwidth as well as jitter tolerance

Table 1: Example I/O Clock Frequency Combinations

◆ Reference clock inputs support differential LVDS,

LVPECL, as well as single-ended LVCMOS, LVTTL

◆ Single 3.3V power supply

◆ Small 9 x 9 mm SMT (surface mount) package

SIMPLIFIED BLOCK DIAGRAM

Loop

Filter

M1010

DIF_REF0

nDIF_REF0

R Div

VCSO

DIF_REF1

nDIF_REF1

M Div

Mfin Div

REF_SEL

FOUT

SEL2:0

Divider LUT

nFOUT

Mfin Divider

LUT

FIN_SEL1:0

Figure 2: Simplified Block Diagram

M1010-01 Datasheet Rev 0.5

Revised 30Mar2005

M1010-01 VCSO Based Clock Jitter Attenuator

Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400

12 3 4 5 6 7 8

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与M1010-01-155.5200LF相关器件

型号	品牌	描述	获取价格	数据表
M1010-01-156.2500	ICSI	VCSO BASED CLOCK JITTER ATTENUATOR	获取价格
M1010-01-156.2500LF	IDT	PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC,	获取价格
M1010-01I155.5200	ICSI	VCSO BASED CLOCK JITTER ATTENUATOR	获取价格
M1010-01I155.5200LF	IDT	PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC,	获取价格
M1010-01I156.2500	ICSI	VCSO BASED CLOCK JITTER ATTENUATOR	获取价格
M1010-01I156.2500LF	IDT	PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC,	获取价格

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