Datasheet > 存储 > SRAM> LY622568LL

LY622568LL

更新时间： 2024-02-14 12:46:16

品牌	Logo	应用领域
台湾来扬 - LYONTEK		静态存储器
页数	文件大小	规格书
14页	217K
描述
256K X 8 BIT LOW POWER CMOS SRAM

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技术参数
数据手册

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LY622568LL 技术参数

生命周期：	Not Recommended	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.8
Is Samacsys：	N	Base Number Matches：	1

LY622568LL 数据手册

LY622568

256K X 8 BIT LOW POWER CMOS SRAM

Rev. 2.2

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

tRC

Address

Dout

tAA

tOH

Previous Data Valid

Data Valid

READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)

tRC

Address

tAA

CE#

t^ACE

CE2

OE#

tOE

tOLZ

tOH

tOHZ

tCHZ

tCLZ

High-Z

Dout

Data Valid

Notes :

1.WE# is high for read cycle.

2.Device is continuously selected OE# = low, CE# = low_.,CE2 = high_.

3.Address must be valid prior to or coincident with CE# = low_,CE2 = high; otherwise t_AAis the limiting parameter.

4.t_CLZ, t_OLZ, t_CHZand t_OHZare specified with C_L= 5pF. Transition is measured ±500mV from steady state.

5.At any given temperature and voltage condition, t_CHZis less than t_CLZ, t_OHZis less than t_OLZ.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

1...3 4 567 8 9...14

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