LXT6051 STM-1/0 SDH Overhead Terminator
Interrupt Handling .................................................................................................................................... ..81
Interrupt Sources ................................................................................................................................ ..81
Interrupt Enables ................................................................................................................................ ..82
Interrupt Clearing ................................................................................................................................ ..82
Status Registers Access ..................................................................................................................... ..82
C2, K3, K2, K1 and S1 Receive Byte Registers Access...................................................................... ..82
Counter Reading ...................................................................................................................................... ..82
Register Address Map ............................................................................................................................. ..83
Global Registers ....................................................................................................................................... ..88
OCR1—Operational Configuration 1 (50H) ............................................................................................. ..88
OCR2—Operational Configuration 2 (51H) ............................................................................................. ..89
CHIP_ID—Chip ID Number (52H) ........................................................................................................... ..90
BUF_ACNTS—Buffer All Counters (54H) ................................................................................................ ..90
Receive Regenerator Section Termination Registers............................................................................ ..91
R_RSTC1—Receive RST Configuration 1 (40H) .................................................................................... ..91
R_RSTC2—Receive RST Configuration 2 (47H) .................................................................................... ..92
LOF_LMN—Loss of Frame L, M, & N Configuration (41–42H) ................................................................ ..92
OOF_ECNT—Out Of Frame Event Counter (44–43H)............................................................................. ..93
B1_ERRCNT—B1 Error Counter (46–45H) ............................................................................................. ..93
Receive Regenerator and Multiplexer Section Termination Registers................................................. ..94
J0_RSTR_C—J0 Expected String Control (0EH) .................................................................................... ..94
J0_RSTR_D—J0 Expected String Data (0FH) ........................................................................................ ..94
WINSZ_SB2—Window Size for Setting ExcB2ErrSt (1C–1BH)................................................................ . 95
CWIN_SB2—Consecutive Windows for Setting ExcB2ErrSt (1DH)......................................................... ..95
E#_EXCWIN—Number of Errs/Win for Excessively Errored Window (1EH)............................................ ..95
WINSZ_C2—Window Size for Clearing ExcB2ErrSt (16–15H) ................................................................ ..95
CWIN_CB2—Consecutive Windows for Clearing ExcB2ErrSt (17H)........................................................ . 96
E#_NEXCWIN—Number of Errs/Win for Non-Excessively Errored Window (18H).................................. ..96
B2_BLKCNT—B2 Block Error Counter (11–10H) .................................................................................... ..96
B2_BIPCNT—B2 BIP Error Counter (14–12H) ........................................................................................ ..96
MR_BLKCNT—MST REI Block Error Counter (0A–09H)......................................................................... ..97
MR_BIPCNT—MST REI BIP Error Counter (0D–0BH) ............................................................................ ..97
R_K1—Received K1 byte (00H) .............................................................................................................. ..97
R_K2—Received K2 Byte (01H) .............................................................................................................. ..97
R_S1—Received S1 byte (02H) .............................................................................................................. ..97
R_NU1_8—Received Nu1_8 byte (03H) ................................................................................................. ..98
R_NU1_9—Received Nu1_9 byte (04H) ................................................................................................. ..98
R_NU2_8—Received Nu2_8 byte (05H) ................................................................................................. ..98
R_NU2__9—Received Nu2_9 byte (06H) ............................................................................................... ..98
R_NU9_8—Received Nu9_8 byte (07H) ................................................................................................. ..98
R_NU9_9—Received Nu9_9 byte (08H) ................................................................................................. ..98
Receive Multiplexer Section Protection Registers................................................................................. ..99
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